Simulation Results: pwrmgr

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 92.96 %
  • assert
  • 98.43 %
  • func
  • 96.54 %
  • line
  • 99.09 %
  • branch
  • 96.38 %
  • cond
  • 95.90 %
  • toggle
  • 99.44 %
  • FSM
  • 74.00 %
Validation stages
V1
83.33%
V2
80.00%
V2S
90.91%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.350s 38.669us 1 1 100.00
csr_hw_reset 0 1 0.00
pwrmgr_csr_hw_reset 3600.018s 0.000us 0 1 0.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.120s 842.923us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.400s 25.185us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.450s 88.007us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
pwrmgr_csr_aliasing 0.400s 25.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.400s 114.032us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.400s 114.032us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.470s 69.151us 1 1 100.00
pwrmgr_lowpower_invalid 0.430s 57.112us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.410s 58.545us 1 1 100.00
pwrmgr_reset_invalid 0.370s 27.311us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.410s 58.545us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.450s 153.611us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.500s 297.550us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.400s 32.275us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 14.320s 10322.073us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.380s 27.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.460s 274.996us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.460s 274.996us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.018s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
pwrmgr_csr_aliasing 0.400s 25.185us 1 1 100.00
pwrmgr_same_csr_outstanding 0.490s 44.196us 1 1 100.00
tl_d_partial_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.018s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
pwrmgr_csr_aliasing 0.400s 25.185us 1 1 100.00
pwrmgr_same_csr_outstanding 0.490s 44.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.850s 192.639us 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.850s 192.639us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.060s 2026.715us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.450s 153.611us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.070s 1646.633us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.540s 75.405us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.370s 30.364us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.110s 658.171us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.390s 34.264us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.017s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.480s 374.901us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.380s 23.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.430s 134.653us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.019s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
pwrmgr_glitch 92110731862590964994228651952211923800870432001772175196060528447881966830060 None
pwrmgr_stress_all_with_rand_reset 71998560263859250606992411400476920191141819316047950913919013665420558635075 None
pwrmgr_csr_hw_reset 61175331089690587818254705166125877658370289644859351233839845353891944375018 None
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks 1 test run
pwrmgr_reset_invalid 37688561049149151917943772116610676778760378712547625384439619691039460813072 95
UVM_INFO @ 27310994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 110157916035504309224877946377325628149146865627493240236104594719622421450284 240
UVM_INFO @ 10322072741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---