Simulation Results: rom_ctrl/192kb

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 92.87 %
  • assert
  • 96.66 %
  • func
  • 97.36 %
  • line
  • 98.95 %
  • branch
  • 98.56 %
  • cond
  • 98.52 %
  • toggle
  • 95.00 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.100s 1092.317us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.100s 94.030us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.260s 124.373us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.740s 193.092us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.320s 64.476us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.570s 82.411us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.260s 124.373us 1 1 100.00
rom_ctrl_csr_aliasing 4.320s 64.476us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.340s 72.216us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.400s 56.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.200s 4.384us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 34.830s 3324.283us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.340s 57.028us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.230s 70.490us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.640s 76.135us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.640s 76.135us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.100s 94.030us 1 1 100.00
rom_ctrl_csr_rw 4.260s 124.373us 1 1 100.00
rom_ctrl_csr_aliasing 4.320s 64.476us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.130s 60.774us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.100s 94.030us 1 1 100.00
rom_ctrl_csr_rw 4.260s 124.373us 1 1 100.00
rom_ctrl_csr_aliasing 4.320s 64.476us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.130s 60.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.290s 5525.124us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
rom_ctrl_tl_intg_err 86.280s 1338.776us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.100s 1092.317us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.100s 1092.317us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.100s 1092.317us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 86.280s 1338.776us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
rom_ctrl_kmac_err_chk 8.340s 57.028us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 184.920s 92924.406us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.290s 5525.124us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 774.680s 876.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 28.240s 13448.775us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 5135040197504771046519200193528955760320946159352694747311884735514479484071 84
UVM_INFO @ 4383501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---