Simulation Results: rstmgr

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 99.20 %
  • assert
  • 98.66 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 0.880s 264.414us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.530s 114.150us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.040s 2813.600us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.500s 69.981us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.950s 195.614us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00
rstmgr_csr_aliasing 0.500s 69.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.500s 155.374us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.240s 472.576us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.960s 303.661us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.610s 1884.175us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.610s 1884.175us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.610s 1884.175us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.610s 1884.175us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.450s 1446.001us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.470s 71.783us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 0.870s 117.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 0.870s 117.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.530s 114.150us 1 1 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00
rstmgr_csr_aliasing 0.500s 69.981us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 264.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.530s 114.150us 1 1 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00
rstmgr_csr_aliasing 0.500s 69.981us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 264.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.220s 18711.223us 1 1 100.00
rstmgr_tl_intg_err 1.110s 495.192us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.220s 18711.223us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.220s 18711.223us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.110s 495.192us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.640s 116.417us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.300s 2562.586us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.660s 301.734us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.220s 18711.223us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.480s 83.453us 1 1 100.00