Simulation Results: rv_timer

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.28 %
  • code
  • 94.26 %
  • assert
  • 98.41 %
  • func
  • 96.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 77.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.460s 146.111us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.290s 14.402us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.300s 14.216us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.180s 89.391us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.300s 70.509us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.830s 129.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.300s 14.216us 1 1 100.00
rv_timer_csr_aliasing 0.300s 70.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.330s 69.248us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.320s 33.056us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 262.150s 338673.941us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 262.150s 338673.941us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.700s 7341.655us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.310s 52.106us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.310s 37.822us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.920s 96.838us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.920s 96.838us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.290s 14.402us 1 1 100.00
rv_timer_csr_rw 0.300s 14.216us 1 1 100.00
rv_timer_csr_aliasing 0.300s 70.509us 1 1 100.00
rv_timer_same_csr_outstanding 0.410s 31.569us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.290s 14.402us 1 1 100.00
rv_timer_csr_rw 0.300s 14.216us 1 1 100.00
rv_timer_csr_aliasing 0.300s 70.509us 1 1 100.00
rv_timer_same_csr_outstanding 0.410s 31.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.450s 477.717us 1 1 100.00
rv_timer_tl_intg_err 0.400s 123.230us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.400s 123.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.350s 238.625us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.420s 43.851us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 28.660s 19250.946us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 11022977051774898069639639493098956459661995795283424203740764389102697377971 84
UVM_INFO @ 238625078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 80559107549783667814114336374302120734894590230089402133087000545180762002389 81
UVM_INFO @ 43850696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---