Simulation Results: spi_device/1r1w

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.52 %
  • code
  • 91.25 %
  • assert
  • 95.40 %
  • func
  • 72.92 %
  • line
  • 98.86 %
  • branch
  • 98.13 %
  • cond
  • 95.58 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 24.110s 4983.408us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.570s 352.262us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.250s 364.491us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 6.590s 278.786us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.250s 121.470us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.430s 50.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.250s 364.491us 1 1 100.00
spi_device_csr_aliasing 1.250s 121.470us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.350s 178.633us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.020s 74.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.400s 62.386us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.380s 1.552us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.380s 5.012us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.780s 122.577us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.780s 122.577us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.390s 6351.294us 1 1 100.00
spi_device_tpm_sts_read 0.380s 17.840us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.330s 15134.408us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.960s 10018.373us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.920s 8804.075us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.920s 8804.075us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 24.200s 5188.229us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 24.200s 5188.229us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 24.200s 5188.229us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 24.200s 5188.229us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 24.200s 5188.229us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.780s 2624.686us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.200s 318.856us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.200s 318.856us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.200s 318.856us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 1.990s 680.721us 1 1 100.00
spi_device_read_buffer_direct 1.540s 157.039us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.200s 318.856us 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 40.690s 38705.181us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.790s 1720.426us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.790s 1720.426us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 65.490s 51050.827us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 24.110s 4983.408us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 48.740s 48277.201us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.890s 283.503us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.380s 19.875us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.400s 67.008us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.130s 263.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.130s 263.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.570s 352.262us 1 1 100.00
spi_device_csr_rw 1.250s 364.491us 1 1 100.00
spi_device_csr_aliasing 1.250s 121.470us 1 1 100.00
spi_device_same_csr_outstanding 2.240s 3384.203us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.570s 352.262us 1 1 100.00
spi_device_csr_rw 1.250s 364.491us 1 1 100.00
spi_device_csr_aliasing 1.250s 121.470us 1 1 100.00
spi_device_same_csr_outstanding 2.240s 3384.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.540s 289.013us 1 1 100.00
spi_device_tl_intg_err 4.130s 2332.917us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.130s 2332.917us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 37371275142634754211501874388764676027855267785820597282976375591631589024011 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 985339 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 985339 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 98050917884728938423263191965495318155038488400942936558376172025953691211235 76
UVM_ERROR @ 2753939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x176 [101110110] vs 0x0 [0])
UVM_ERROR @ 2843939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ce [1011001110] vs 0x0 [0])
UVM_ERROR @ 2927939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2af [1010101111] vs 0x0 [0])
UVM_ERROR @ 2979939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x213 [1000010011] vs 0x0 [0])