Simulation Results: spi_host

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.42 %
  • code
  • 91.30 %
  • assert
  • 94.71 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 195.480us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 4.000s 49.132us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 4.000s 20.337us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 533.761us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 4.000s 25.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 4.000s 25.454us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 4.000s 20.337us 1 1 100.00
spi_host_csr_aliasing 4.000s 25.143us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 4.000s 107.029us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 4.000s 24.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 4.000s 59.676us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 94.020us 1 1 100.00
spi_host_error_cmd 4.000s 19.078us 1 1 100.00
spi_host_event 8.000s 4380.428us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 59.697us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 59.697us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 59.697us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 39.000s 2513.749us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 289.942us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 4.000s 23.758us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 59.697us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 59.697us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 195.480us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 195.480us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 830.000s 1000000.000us 0 1 0.00
spien 1 1 100.00
spi_host_spien 1.000s 596.182us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 106.000s 61186.769us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 13.000s 9335.489us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 94.020us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 4.000s 21.057us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 4.000s 25.386us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 438.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 438.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 49.132us 1 1 100.00
spi_host_csr_rw 4.000s 20.337us 1 1 100.00
spi_host_csr_aliasing 4.000s 25.143us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 182.714us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 49.132us 1 1 100.00
spi_host_csr_rw 4.000s 20.337us 1 1 100.00
spi_host_csr_aliasing 4.000s 25.143us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 182.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 57.096us 1 1 100.00
spi_host_sec_cm 1.000s 129.114us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 57.096us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_stress_all 108184084414155350790977157301996603709074641925669739502927488661996519258414 155
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---