Simulation Results: sram_ctrl/main

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 95.06 %
  • assert
  • 98.10 %
  • func
  • 94.60 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.75 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 369.489us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 24.254us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.062us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 581.687us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 714.219us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.062us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.217us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 99.000s 11119.103us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 98.000s 20175.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 15941.966us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 120.000s 19773.200us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 109.000s 22453.351us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 36.000s 41881.873us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.000s 31981.142us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 25.000s 13320.661us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2677.634us 1 1 100.00
sram_ctrl_partial_access_b2b 121.000s 47094.772us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 689.369us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 1332.982us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 1339.685us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 987.277us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1403.680us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 3.000s 369.489us 1 1 100.00
sram_ctrl_partial_access 4.000s 2677.634us 1 1 100.00
sram_ctrl_access_during_key_req 36.000s 41881.873us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 36.000s 21905.013us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.000s 26.880us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 45.967us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 45.967us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.254us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.062us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.217us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 17.407us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.254us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.062us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.217us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 17.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 24300.261us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 310.502us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 310.502us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 987.277us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 987.277us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.062us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 25.000s 13320.661us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 13320.661us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 13320.661us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.000s 31981.142us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 24300.261us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 369.489us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 369.489us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 25.000s 13320.661us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.000s 31981.142us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 369.489us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1271.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 385.193us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 59717618535310091294593696995169996870718236594165234504258584069526880019830 None
sram_ctrl_mubi_enc_err 11162193221818897291582768291433512949760408496819549038777772590732836399078 None