Simulation Results: sram_ctrl/ret

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.19 %
  • code
  • 80.83 %
  • assert
  • 97.95 %
  • func
  • 91.80 %
  • block
  • 91.03 %
  • line
  • 92.28 %
  • branch
  • 86.03 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 28.314us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 84.816us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.063us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 448.593us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.320us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 37.132us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.320us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 386.416us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 219.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 385.682us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 91.000s 4052.677us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 9205.154us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 583.898us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 1.000s 1228.397us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 572.289us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 47.876us 1 1 100.00
sram_ctrl_partial_access_b2b 185.000s 67831.498us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 115.058us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 668.671us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 72.949us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 219.240us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 54.573us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 28.314us 1 1 100.00
sram_ctrl_partial_access 1.000s 47.876us 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 583.898us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 13.000s 2811.854us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.721us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 147.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 147.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.816us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.320us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 58.336us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.816us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.320us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 58.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 373.449us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 486.740us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 486.740us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 219.240us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 219.240us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.063us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 572.289us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 572.289us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 572.289us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 1.000s 1228.397us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 373.449us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 28.314us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 28.314us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 572.289us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 1.000s 1228.397us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 28.314us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 5133.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 5.000s 405.245us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 32702831951132332076371374160197261884315200899524192531230692370792470881645 None
sram_ctrl_mubi_enc_err 103413636691465019952877994062362380859966290968118506040553305325809935230456 None
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 89394819593989896645365542250762446923971960229257113201805083630017445727421 148
UVM_INFO @ 405245178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---