Simulation Results: sysrst_ctrl

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.43 %
  • code
  • 92.36 %
  • assert
  • 93.56 %
  • func
  • 64.37 %
  • line
  • 96.89 %
  • branch
  • 97.22 %
  • cond
  • 94.18 %
  • toggle
  • 99.77 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 0.840s 2131.974us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 0.930s 2470.359us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.860s 2280.040us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.060s 2530.373us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.440s 4070.798us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.700s 2063.490us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 3.600s 6162.796us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 1.970s 2041.283us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.930s 2074.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.700s 2063.490us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.970s 2041.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 10.610s 50219.053us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 13.890s 24841.533us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.660s 3139.521us 1 1 100.00
keyboard_input_triggered_interrupt 0 1 0.00
sysrst_ctrl_edge_detect 2.810s 2328.070us 0 1 0.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 0.770s 2559.766us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.990s 2216.556us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 0.790s 3053.278us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.160s 2629.712us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 2.520s 2442.757us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 38.280s 36203.658us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.910s 9001.785us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.650s 2041.219us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.230s 2013.401us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.470s 2802.636us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.470s 2802.636us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.440s 4070.798us 1 1 100.00
sysrst_ctrl_csr_rw 2.700s 2063.490us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.970s 2041.283us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.370s 5105.146us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.440s 4070.798us 1 1 100.00
sysrst_ctrl_csr_rw 2.700s 2063.490us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.970s 2041.283us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.370s 5105.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 24.440s 22010.726us 1 1 100.00
sysrst_ctrl_tl_intg_err 47.780s 42489.683us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 47.780s 42489.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.390s 13438.936us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 2 test runs
sysrst_ctrl_ultra_low_pwr 61406736070200345872944520286068657330910359762667280720316943893376059462774 661
UVM_ERROR @ 2442756732 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2442756732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_edge_detect 84702469240354463407153056705357001834667806535804610566460874970844551110399 662
UVM_ERROR @ 2328070479 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2328070479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---