Simulation Results: uart

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 82.41 %
  • code
  • 90.71 %
  • assert
  • 97.12 %
  • func
  • 59.41 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.00 %
  • toggle
  • 74.49 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.410s 129.242us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.890s 1033.538us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.330s 57.091us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 0.830s 764.354us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.330s 23.279us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.460s 126.474us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.330s 57.091us 1 1 100.00
uart_csr_aliasing 0.330s 23.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 11.300s 78540.996us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.410s 129.242us 1 1 100.00
uart_tx_rx 11.300s 78540.996us 1 1 100.00
parity_error 2 2 100.00
uart_intr 1.940s 3136.823us 1 1 100.00
uart_rx_parity_err 24.520s 30190.128us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 11.300s 78540.996us 1 1 100.00
uart_intr 1.940s 3136.823us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 11.960s 105752.683us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 9.950s 110712.983us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 35.730s 117207.285us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 1.940s 3136.823us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 1.940s 3136.823us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 1.940s 3136.823us 1 1 100.00
perf 1 1 100.00
uart_perf 240.520s 18940.745us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.350s 7395.723us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.350s 7395.723us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.240s 58337.454us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.560s 1544.079us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 0.680s 398.673us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.680s 1592.619us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 126.860s 82756.029us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 35.310s 181808.604us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.320s 40.573us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.330s 16.984us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.940s 99.714us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.940s 99.714us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.890s 1033.538us 1 1 100.00
uart_csr_rw 0.330s 57.091us 1 1 100.00
uart_csr_aliasing 0.330s 23.279us 1 1 100.00
uart_same_csr_outstanding 0.390s 103.810us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.890s 1033.538us 1 1 100.00
uart_csr_rw 0.330s 57.091us 1 1 100.00
uart_csr_aliasing 0.330s 23.279us 1 1 100.00
uart_same_csr_outstanding 0.390s 103.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.410s 136.959us 1 1 100.00
uart_tl_intg_err 0.690s 111.309us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.690s 111.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 12.210s 1494.621us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 113382869502786349953897300997907293222067936424505671645081838356787173557419 84
UVM_ERROR @ 55682174103 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 55682907440 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 123 [0x7b]) reg name: uart_reg_block.rdata
UVM_ERROR @ 55683040774 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 55683107441 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata