Simulation Results: adc_ctrl

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.31 %
  • code
  • 96.22 %
  • assert
  • 96.27 %
  • func
  • 18.44 %
  • line
  • 99.05 %
  • branch
  • 98.45 %
  • cond
  • 94.42 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 6.110s 5664.461us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.900s 1254.267us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.740s 451.453us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 46.870s 26715.545us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 0.760s 414.853us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.720s 531.942us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.740s 451.453us 1 1 100.00
adc_ctrl_csr_aliasing 0.760s 414.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 27.030s 53866.293us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 9.670s 34358.094us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 61.890s 54149.783us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 8.540s 38143.990us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 15.040s 24401.553us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 54.010s 46001.218us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 5.050s 44964.106us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.140s 21798.916us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.530s 5201.999us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 9.810s 31440.571us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 18.080s 66238.745us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 9.320s 30055.340us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.480s 437.246us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.750s 433.514us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 0.850s 682.359us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 0.850s 682.359us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.900s 1254.267us 1 1 100.00
adc_ctrl_csr_rw 0.740s 451.453us 1 1 100.00
adc_ctrl_csr_aliasing 0.760s 414.853us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.470s 4165.529us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.900s 1254.267us 1 1 100.00
adc_ctrl_csr_rw 0.740s 451.453us 1 1 100.00
adc_ctrl_csr_aliasing 0.760s 414.853us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.470s 4165.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.870s 3865.541us 1 1 100.00
adc_ctrl_tl_intg_err 6.120s 4542.718us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.120s 4542.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.940s 2175.498us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 2 test runs
adc_ctrl_clock_gating 11038809148444328807544614070696808486485562148386854424561692755210804702662 399
UVM_INFO @ 21798915744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 62845628540333283810705321611905402540765769485357980843717612782186615755956 405
UVM_INFO @ 2175498334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---