Simulation Results: aes/masked

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.97 %
  • code
  • 94.06 %
  • assert
  • 98.23 %
  • func
  • 77.63 %
  • block
  • 94.14 %
  • line
  • 95.72 %
  • branch
  • 86.97 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 70.020us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 99.122us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 0.000s 93.448us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 111.896us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 995.632us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 145.135us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 240.917us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 111.896us 1 1 100.00
aes_csr_aliasing 1.000s 145.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 99.122us 1 1 100.00
aes_config_error 2.000s 347.803us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 99.122us 1 1 100.00
aes_config_error 2.000s 347.803us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_b2b 11.000s 525.939us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 99.122us 1 1 100.00
aes_config_error 2.000s 347.803us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 66.582us 1 1 100.00
aes_config_error 2.000s 347.803us 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 160.886us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 385.487us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_sideload 2.000s 782.008us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 88.319us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 26.000s 851.903us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 97.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 258.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 258.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 0.000s 93.448us 1 1 100.00
aes_csr_rw 1.000s 111.896us 1 1 100.00
aes_csr_aliasing 1.000s 145.135us 1 1 100.00
aes_same_csr_outstanding 1.000s 132.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 0.000s 93.448us 1 1 100.00
aes_csr_rw 1.000s 111.896us 1 1 100.00
aes_csr_aliasing 1.000s 145.135us 1 1 100.00
aes_same_csr_outstanding 1.000s 132.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 115.796us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 1.000s 257.942us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 398.381us 1 1 100.00
aes_tl_intg_err 1.000s 274.030us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 274.030us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 99.122us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
aes_core_fi 1.000s 318.877us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 347.803us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_core_fi 1.000s 318.877us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 285.584us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 67.961us 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 134.298us 1 1 100.00
aes_sideload 2.000s 782.008us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 67.961us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 67.961us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 67.961us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 67.961us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 67.961us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 134.298us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.366us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.366us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.366us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.366us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 336.070us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_ctr_fi 1.000s 74.964us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 194.366us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 194.366us 0 1 0.00
aes_control_fi 34.000s 10006.912us 0 1 0.00
aes_cipher_fi 1.000s 47.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 25.000s 3345.596us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 20091711110752083697918664407736041560370838071201822174463015745084333673897 11214
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 102998776042746506512644559948964271615720608871865278298455242519417232724323 145
UVM_INFO @ 10006911553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 95469230275611926322884088732869056769346237464366480525018114764071771203096 539
UVM_INFO @ 3345595693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---