Simulation Results: aes/unmasked

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.37 %
  • code
  • 89.81 %
  • assert
  • 97.73 %
  • func
  • 74.57 %
  • block
  • 89.70 %
  • line
  • 92.03 %
  • branch
  • 80.40 %
  • toggle
  • 97.90 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 83.891us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 123.553us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 117.987us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 56.878us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 2945.939us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 0.000s 134.807us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 67.228us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 56.878us 1 1 100.00
aes_csr_aliasing 0.000s 134.807us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 123.553us 1 1 100.00
aes_config_error 1.000s 121.463us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 123.553us 1 1 100.00
aes_config_error 1.000s 121.463us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_b2b 3.000s 100.883us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 123.553us 1 1 100.00
aes_config_error 1.000s 121.463us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 82.859us 1 1 100.00
aes_config_error 1.000s 121.463us 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 1.000s 75.600us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 2.000s 209.124us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_sideload 1.000s 134.053us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 65.490us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 2.000s 162.179us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 58.883us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 87.511us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 87.511us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 117.987us 1 1 100.00
aes_csr_rw 1.000s 56.878us 1 1 100.00
aes_csr_aliasing 0.000s 134.807us 1 1 100.00
aes_same_csr_outstanding 1.000s 209.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 117.987us 1 1 100.00
aes_csr_rw 1.000s 56.878us 1 1 100.00
aes_csr_aliasing 0.000s 134.807us 1 1 100.00
aes_same_csr_outstanding 1.000s 209.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 1.000s 127.765us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
shadow_reg_update_error 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 1.000s 102.885us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 441.665us 1 1 100.00
aes_tl_intg_err 2.000s 116.597us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 116.597us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
sec_cm_main_config_shadow 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
sec_cm_gcm_config_shadow 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 123.553us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
aes_core_fi 1.000s 111.031us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 1.000s 121.463us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_core_fi 1.000s 111.031us 1 1 100.00
sec_cm_aux_config_shadow 0 1 0.00
aes_shadow_reg_errors 12.000s 10036.543us 0 1 0.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 207.148us 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 74.848us 1 1 100.00
aes_sideload 1.000s 134.053us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 207.148us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 207.148us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 207.148us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 207.148us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 207.148us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 74.848us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 78.482us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 78.482us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 78.482us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 78.482us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 585.221us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_ctr_fi 1.000s 106.056us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 78.482us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 78.482us 0 1 0.00
aes_control_fi 1.000s 57.424us 1 1 100.00
aes_cipher_fi 0.000s 70.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 826.636us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 70043559559403858454678660363436535214569779334003798635055021836565960715143 5415
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:782) scoreboard [scoreboard] # * 1 test run
aes_stress_all 98573625893152055477385509288136858946824711538952564414233915911274717460275 17834
TEST FAILED MESSAGES DID NOT MATCH
0 c6 1a 1a 0
1 00 0b 0b 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 85906324423478494607647995022739932910128404678068637789026098380622490943491 517
UVM_INFO @ 826635718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors 20731612006891038833411058528333323234201173749721783190138472128766479782416 107
UVM_INFO @ 10036542520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---