| V1 |
|
100.00% |
| V2 |
|
89.47% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 1.990s | 41.824us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_csr_rw | 5.340s | 116.987us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 186.180s | 2580.493us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 56.250s | 3382.452us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 2.640s | 37.494us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| alert_handler_csr_rw | 5.340s | 116.987us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 56.250s | 3382.452us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 39.860s | 2227.610us | 1 | 1 | 100.00 | |
| esc_timeout | 1 | 1 | 100.00 | |||
| alert_handler_esc_intr_timeout | 7.130s | 737.819us | 1 | 1 | 100.00 | |
| entropy | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 878.200s | 223414.019us | 1 | 1 | 100.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 22.630s | 345.585us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 42.490s | 1083.352us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 21.400s | 831.437us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 39.850s | 6852.459us | 0 | 1 | 0.00 | |
| lpg | 2 | 2 | 100.00 | |||
| alert_handler_lpg | 1390.440s | 51973.172us | 1 | 1 | 100.00 | |
| alert_handler_lpg_stub_clk | 919.530s | 137831.986us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| alert_handler_stress_all | 1522.000s | 219597.492us | 1 | 1 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 1 | 0.00 | |||
| alert_handler_entropy_stress | 19.190s | 777.980us | 0 | 1 | 0.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 2.010s | 128.263us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| alert_handler_intr_test | 0.970s | 11.151us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 11.540s | 455.324us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 11.540s | 455.324us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 1.990s | 41.824us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 5.340s | 116.987us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 56.250s | 3382.452us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 26.370s | 2699.052us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 1.990s | 41.824us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 5.340s | 116.987us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 56.250s | 3382.452us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 26.370s | 2699.052us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 81.040s | 6565.625us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 81.040s | 6565.625us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 81.040s | 6565.625us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 81.040s | 6565.625us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 299.750s | 7878.476us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| alert_handler_tl_intg_err | 51.870s | 5001.454us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| alert_handler_tl_intg_err | 51.870s | 5001.454us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 81.040s | 6565.625us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 37.050s | 1172.485us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 22.630s | 345.585us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 1 | 1 | 100.00 | |||
| alert_handler_lpg | 1390.440s | 51973.172us | 1 | 1 | 100.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 22.630s | 345.585us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 878.200s | 223414.019us | 1 | 1 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 878.200s | 223414.019us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_accu_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.140s | 189.594us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_stress_all_with_rand_reset | 252.160s | 4557.613us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 1 test run | |||
| alert_handler_ping_timeout | 105746914282515334783305052904307338069356810423918311955539603269019216079721 | 105 |
UVM_INFO @ 6852459104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 1 test run | |||
| alert_handler_entropy_stress | 107481022149318847796583954590022713858447324892330898032169559144650685520342 | 212 |
UVM_INFO @ 777980015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|