Simulation Results

Simulation Results: chip

14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
67.75 %

code
75.94 %

assert
96.86 %

func
30.45 %

line
93.57 %

branch
93.24 %

cond
89.21 %

toggle
70.34 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		85.17%
V2S		100.00%
V3		56.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	72.040s	2009.986us	1	1	100.00
	chip_sw_example_manufacturer	184.560s	2693.024us	1	1	100.00
	chip_sw_example_concurrency	162.400s	2500.206us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	404.890s	12000.420us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	426.530s	10808.798us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	283.900s	9313.558us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	7838.870s	69982.011us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	774.180s	13402.769us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	7838.870s	69982.011us	1	1	100.00
	chip_csr_rw	426.530s	10808.798us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	2.750s	40.700us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	302.100s	4021.041us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	302.100s	4021.041us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	302.100s	4021.041us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	327.890s	4216.764us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	327.890s	4216.764us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	348.540s	3942.552us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	345.630s	4022.230us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	349.450s	4294.751us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1728.370s	12773.787us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	346.690s	4015.987us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	529.090s	8248.159us	1	1	100.00

224/263 passed

85.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	248.720s	7543.282us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	248.720s	7543.282us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	213.830s	2899.936us	1	1	100.00
chip_sw_sleep_pin_wake				0	1	0.00
	chip_sw_sleep_pin_wake	147.830s	2694.554us	0	1	0.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	191.290s	3225.906us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	141.570s	3369.260us	1	1	100.00
	chip_tap_straps_testunlock0	209.530s	5346.149us	1	1	100.00
	chip_tap_straps_rma	377.940s	7137.834us	1	1	100.00
	chip_tap_straps_prod	1108.950s	18998.667us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	391.460s	4732.739us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	391.460s	4732.739us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	629.900s	6860.125us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	747.130s	8301.198us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3703.430s	18998.373us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.940s	2445.254us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	671.800s	6166.238us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.920s	3061.241us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1686.050s	11441.847us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.110s	3240.966us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	413.390s	4500.858us	1	1	100.00
	chip_sw_clkmgr_jitter	129.860s	2736.710us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	194.240s	2880.680us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	269.130s	3822.790us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	142.640s	2332.543us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	168.110s	2451.413us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	142.640s	2332.543us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	193.580s	2860.714us	1	1	100.00
	chip_sw_aon_timer_smoketest	211.620s	3183.059us	1	1	100.00
	chip_sw_clkmgr_smoketest	150.910s	2566.362us	1	1	100.00
	chip_sw_csrng_smoketest	171.680s	2734.102us	1	1	100.00
	chip_sw_entropy_src_smoketest	993.310s	7473.414us	1	1	100.00
	chip_sw_gpio_smoketest	175.360s	3079.249us	1	1	100.00
	chip_sw_hmac_smoketest	213.080s	3299.662us	1	1	100.00
	chip_sw_kmac_smoketest	207.690s	3123.446us	1	1	100.00
	chip_sw_otbn_smoketest	1272.580s	9216.393us	1	1	100.00
	chip_sw_pwrmgr_smoketest	343.640s	5553.614us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	275.550s	5735.548us	1	1	100.00
	chip_sw_rv_plic_smoketest	176.420s	2443.246us	1	1	100.00
	chip_sw_rv_timer_smoketest	210.970s	2535.436us	1	1	100.00
	chip_sw_rstmgr_smoketest	196.540s	2798.261us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	123.060s	2497.169us	1	1	100.00
	chip_sw_uart_smoketest	126.840s	2754.138us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	144.290s	2607.856us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	280.470s	3796.535us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	18068.700s	127844.718us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3122.240s	14980.864us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	985.100s	19028.245us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	368.460s	3705.370us	1	1	100.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	142.570s	3547.685us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.041s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	247.550s	10248.169us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	247.550s	10248.169us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	7838.870s	69982.011us	1	1	100.00
	chip_same_csr_outstanding	2681.760s	28716.365us	1	1	100.00
	chip_csr_hw_reset	404.890s	12000.420us	1	1	100.00
	chip_csr_rw	426.530s	10808.798us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	7838.870s	69982.011us	1	1	100.00
	chip_same_csr_outstanding	2681.760s	28716.365us	1	1	100.00
	chip_csr_hw_reset	404.890s	12000.420us	1	1	100.00
	chip_csr_rw	426.530s	10808.798us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	12.790s	453.653us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	2.960s	41.664us	1	1	100.00
	xbar_smoke_large_delays	30.870s	7689.036us	1	1	100.00
	xbar_smoke_slow_rsp	30.860s	5154.692us	1	1	100.00
	xbar_random_zero_delays	3.340s	39.873us	1	1	100.00
	xbar_random_large_delays	160.040s	40055.013us	1	1	100.00
	xbar_random_slow_rsp	40.840s	6493.680us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	27.650s	1089.051us	1	1	100.00
	xbar_error_and_unmapped_addr	7.460s	100.478us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	2.990s	27.756us	1	1	100.00
	xbar_error_and_unmapped_addr	7.460s	100.478us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	17.380s	417.831us	1	1	100.00
	xbar_access_same_device_slow_rsp	83.800s	14352.762us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	5.140s	197.182us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	154.290s	6714.431us	1	1	100.00
	xbar_stress_all_with_error	72.510s	2650.736us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	168.060s	1234.491us	1	1	100.00
	xbar_stress_all_with_reset_error	67.120s	634.833us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3122.240s	14980.864us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	2048.350s	25355.487us	0	1	0.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3633.140s	29703.454us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2363.550s	11134.073us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3275.480s	16613.295us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3430.900s	15935.171us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3385.790s	15600.263us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3109.100s	15479.143us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2378.090s	11655.885us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3358.990s	15599.701us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3283.080s	15777.202us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3289.870s	16929.292us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3237.220s	16752.491us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	4551.250s	17889.211us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	5751.000s	24889.546us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	5814.010s	24790.350us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	5870.090s	24295.444us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	5658.160s	23013.270us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	4571.390s	17161.767us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	5956.320s	27231.953us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	5903.740s	26783.752us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	5619.900s	22304.013us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	5903.550s	31063.428us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2425.550s	10090.926us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3064.250s	14156.784us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3130.520s	24690.809us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	3143.730s	13724.006us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3053.300s	13390.376us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2473.320s	17390.663us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3221.370s	15379.176us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3074.760s	19925.214us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3393.200s	22571.231us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3372.820s	24651.116us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2434.260s	11072.702us	1	1	100.00
	rom_e2e_asm_init_dev	3378.070s	15737.136us	1	1	100.00
	rom_e2e_asm_init_prod	3357.180s	16087.516us	1	1	100.00
	rom_e2e_asm_init_prod_end	3360.180s	15758.404us	1	1	100.00
	rom_e2e_asm_init_rma	3202.530s	15135.359us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	6502.520s	29058.405us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	6450.180s	29593.094us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	6581.350s	30583.927us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3344.310s	16682.927us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3002.290s	34710.224us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3002.290s	34710.224us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	148.760s	2397.141us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.940s	2445.254us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	181.140s	2926.168us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	149.730s	2692.393us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1029.890s	8902.998us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	177.470s	2885.913us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	297.500s	4916.896us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	495.430s	4803.499us	1	1	100.00
	chip_plic_all_irqs_10	235.520s	3316.528us	1	1	100.00
	chip_plic_all_irqs_20	326.760s	3662.622us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	221.610s	3344.004us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1077.090s	13716.886us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	237.200s	4653.975us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	143.510s	3107.963us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	231.970s	2757.444us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	829.140s	6930.198us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1094.840s	8247.120us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	875.370s	7881.877us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8230.360s	255086.637us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	231.710s	3445.256us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	343.640s	5553.614us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	231.710s	3445.256us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	408.340s	7247.377us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	408.340s	7247.377us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	242.770s	6351.901us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	341.320s	4692.642us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	666.860s	5793.347us	1	1	100.00
	chip_sw_aes_idle	149.730s	2692.393us	1	1	100.00
	chip_sw_hmac_enc_idle	195.110s	2868.907us	1	1	100.00
	chip_sw_kmac_idle	137.970s	2889.403us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	235.960s	3910.762us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	230.480s	4027.139us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	277.340s	4006.667us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	216.810s	3075.667us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	898.040s	10522.729us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	374.590s	4386.404us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	391.350s	4777.114us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.030s	4226.181us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	409.550s	5220.207us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	358.940s	3351.077us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	357.830s	4811.701us	1	1	100.00
	chip_sw_ast_clk_outputs	629.900s	6860.125us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1165.350s	27368.728us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.030s	4226.181us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	409.550s	5220.207us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3703.430s	18998.373us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.940s	2445.254us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	671.800s	6166.238us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.920s	3061.241us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1686.050s	11441.847us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.110s	3240.966us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	413.390s	4500.858us	1	1	100.00
	chip_sw_clkmgr_jitter	129.860s	2736.710us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	173.270s	3133.068us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3948.410s	25073.564us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	152.160s	2751.290us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	170.760s	3460.870us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1039.340s	10656.698us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	217.350s	3498.680us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	314.300s	4836.803us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	14845.220s	159455.548us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	629.900s	6860.125us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	335.780s	4022.802us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	479.350s	9063.530us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	829.140s	6930.198us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1882.570s	24246.932us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	282.240s	3650.249us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	560.280s	8470.990us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	176.790s	3245.796us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2138.910s	13651.838us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	183.910s	2696.647us	1	1	100.00
	chip_sw_edn_entropy_reqs	822.340s	7153.164us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	183.910s	2696.647us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1882.570s	24246.932us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	158.080s	2593.909us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	133.610s	2534.689us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.920s	3061.241us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	195.110s	2868.907us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	932.760s	6716.350us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1831.010s	12010.180us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	401.790s	4967.253us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	433.830s	4790.185us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	410.130s	4769.493us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	303.770s	3722.776us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	2016.530s	12770.491us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1686.050s	11441.847us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	720.640s	6512.957us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1029.890s	8902.998us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.038s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	155.170s	3250.223us	1	1	100.00
	chip_sw_kmac_mode_kmac	205.080s	2796.318us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.110s	3240.966us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2016.530s	12770.491us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	336.440s	8161.036us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	831.310s	6155.561us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	137.970s	2889.403us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	297.500s	4916.896us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	141.570s	3369.260us	1	1	100.00
	chip_tap_straps_rma	377.940s	7137.834us	1	1	100.00
	chip_tap_straps_prod	1108.950s	18998.667us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	134.140s	2597.402us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	780.690s	6973.330us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	188.280s	10010.160us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	240.990s	3129.213us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	485.620s	6930.664us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	563.530s	6315.800us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	572.100s	6572.876us	0	1	0.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	364.940s	5375.100us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2016.530s	12770.491us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	627.460s	23131.840us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	582.170s	8366.603us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1165.350s	27368.728us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	374.590s	4386.404us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	391.350s	4777.114us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.030s	4226.181us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	409.550s	5220.207us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	358.940s	3351.077us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	357.830s	4811.701us	1	1	100.00
	chip_tap_straps_dev	141.570s	3369.260us	1	1	100.00
	chip_tap_straps_rma	377.940s	7137.834us	1	1	100.00
	chip_tap_straps_prod	1108.950s	18998.667us	1	1	100.00
	chip_rv_dm_lc_disabled	69.170s	3619.863us	0	1	0.00
chip_lc_scrap				3	4	75.00
	chip_sw_lc_ctrl_rma_to_scrap	294.080s	5367.853us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	252.990s	7255.171us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	395.400s	10466.985us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	336.110s	5211.490us	1	1	100.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	2246.700s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	69.170s	3619.863us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1125.010s	19225.823us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1241.560s	16758.719us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	932.130s	17309.241us	1	1	100.00
	chip_sw_lc_walkthrough_rma	625.710s	10052.890us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2246.700s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	142.260s	4534.236us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	168.550s	5912.023us	1	1	100.00
	rom_volatile_raw_unlock	176.930s	6058.856us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3637.470s	17746.134us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3703.430s	18998.373us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	666.860s	5793.347us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	666.860s	5793.347us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	666.860s	5793.347us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	322.020s	3096.222us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	322.020s	3096.222us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2016.530s	12770.491us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	374.720s	4943.620us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2459.300s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	322.020s	3096.222us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2016.530s	12770.491us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	374.720s	4943.620us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2459.300s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	396.050s	5785.298us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	134.140s	2597.402us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	240.990s	3129.213us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	485.620s	6930.664us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	563.530s	6315.800us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	572.100s	6572.876us	0	1	0.00
	chip_sw_lc_ctrl_transition	674.640s	15519.784us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	808.940s	6542.365us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	280.240s	7927.378us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	106.650s	2825.575us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	137.560s	2428.309us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	490.460s	8496.359us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	373.570s	4643.846us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	993.290s	21999.499us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1050.340s	12924.389us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	408.340s	7247.377us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	193.460s	4442.921us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	334.810s	4041.307us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	280.240s	7927.378us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	246.880s	3448.799us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	170.390s	3280.153us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	359.750s	7180.792us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	168.120s	3158.445us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	368.160s	8025.323us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	547.290s	6033.400us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	848.680s	8960.525us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1160.380s	19455.895us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	138.910s	3292.474us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	627.460s	23131.840us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	627.460s	23131.840us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	848.680s	8960.525us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	368.160s	8025.323us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	334.810s	4041.307us	1	1	100.00
	chip_sw_pwrmgr_smoketest	343.640s	5553.614us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	341.490s	4544.662us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	308.930s	4006.669us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	316.440s	3555.904us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1077.090s	13716.886us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	132.980s	2490.522us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1094.840s	8247.120us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	428.050s	4909.278us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	529.150s	4962.681us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	196.030s	3262.804us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	2459.300s	60000.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	308.930s	4006.669us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	308.930s	4006.669us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	119.210s	2808.610us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	67.980s	2441.474us	0	1	0.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1118.240s	24515.259us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	341.490s	4544.662us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	178.280s	3173.462us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	158.130s	2880.306us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	377.940s	7137.834us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	69.170s	3619.863us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	495.430s	4803.499us	1	1	100.00
	chip_plic_all_irqs_10	235.520s	3316.528us	1	1	100.00
	chip_plic_all_irqs_20	326.760s	3662.622us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	160.180s	2604.807us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	178.060s	3023.830us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3122.240s	14980.864us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	414.510s	6095.036us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	189.270s	2747.722us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	245.670s	3247.296us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	179.530s	2643.374us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	374.720s	4943.620us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	413.390s	4500.858us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	200.180s	3361.369us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	171.840s	3231.955us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	582.170s	8366.603us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
	chip_sw_data_integrity_escalation	391.460s	4732.739us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	547.290s	6033.400us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	923.440s	22269.446us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	181.160s	2722.371us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	195.000s	3608.954us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	279.010s	3843.996us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	923.440s	22269.446us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	923.440s	22269.446us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2447.580s	20681.064us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2447.580s	20681.064us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	349.040s	5713.742us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3002.290s	34710.224us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	159.410s	2649.386us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	149.070s	2446.709us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	244.900s	3241.211us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	301.030s	3405.926us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	864.850s	8095.097us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5440.410s	31626.072us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1948.110s	11962.002us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	185.380s	2810.146us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	165.890s	3040.308us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	156.880s	2924.346us	1	1	100.00

14/25 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	11034.070s	72177.164us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1091.200s	6644.473us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	49.970s	2259.432us	0	1	0.00
	rom_e2e_jtag_debug_dev	53.740s	1945.451us	0	1	0.00
	rom_e2e_jtag_debug_rma	56.060s	2176.728us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	49.100s	1867.091us	0	1	0.00
	rom_e2e_jtag_inject_dev	52.050s	2137.099us	0	1	0.00
	rom_e2e_jtag_inject_rma	61.120s	2000.889us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	126.981s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	287.510s	3680.576us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	312.640s	2753.593us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1107.990s	6224.018us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	684.690s	6214.964us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	231.750s	2621.941us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	199.880s	3634.836us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	230.100s	4976.084us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	263.850s	4262.032us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	848.680s	8960.525us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	336.440s	8161.036us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	49.970s	2259.432us	0	1	0.00
	rom_e2e_jtag_debug_dev	53.740s	1945.451us	0	1	0.00
	rom_e2e_jtag_debug_rma	56.060s	2176.728us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	202.450s	3167.040us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	381.300s	5638.517us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5618.660s	38042.823us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5618.660s	38042.823us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	175.450s	2913.086us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	327.890s	4216.764us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3055.650s	18626.935us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	28.610s	10.360us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	55.990s	2104.547us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	223.800s	2838.381us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	187.840s	3422.403us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	6.317s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	441.120s	10010.100us	0	1	0.00
	ate_bootstrap_one_frame	10800.047s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.052s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				16 test runs
	chip_sw_sleep_pin_wake	40152721610243606020532904952745942062412484824545022689470616694649951902390	382	UVM_INFO @ 2694.553854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_pin_retention	17458620217188480724703213584628503173237656448711934844447119797449489666147	379	UVM_INFO @ 3225.906456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	60347243139598335647198218504190814570409417602620467251547131679044823212227	374	UVM_INFO @ 2913.086400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	16654825065958295702185730235558586401306119675630970917289597664392147561448	392	UVM_INFO @ 8025.323084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	108052291537356623148599811805536805951910500917146794522284783506834750534791	377	UVM_INFO @ 4442.920666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	10247583602562539607706216351580340958931431242026399019177562587993349119930	388	UVM_INFO @ 4643.845569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	87029307731007326595059925567555681101091356569185966549988679876113714286581	379	UVM_INFO @ 3280.153450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	107473617756889719119529869550578165509093011629748692538922441314958364630016	377	UVM_INFO @ 3361.368564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	5729691430790291175800716288032647915479156239066044746414961930266952982796	381	UVM_INFO @ 3231.954940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	55686141728873031194994780129850076696381847149443676255704191971556916223231	372	UVM_INFO @ 2332.542740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	65000387499022066742656914466980703366930934336701206643568346640857884010477	407	UVM_INFO @ 4022.801534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	80484644177526103468925604745437700827407435549419772033611454830532914846335	374	UVM_INFO @ 2428.309008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	7318446678219743185524559746325923527041840661658985614778599856971663885539	372	UVM_INFO @ 3422.402790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	61734041866665135847598724503236050135861480182434945950469359084149766644694	373	UVM_INFO @ 2825.575366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	1936685649302069690540181675985522728215731873240201901557208342354794057920	390	UVM_INFO @ 2880.305514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_power_sleep_load	38289054684540805433095804768877049684475306553513679343946546736378965417365	387	UVM_INFO @ 3547.684686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	30087837501979446281333278418128669388648300760937488622626516367630280330427	386	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	2348542257684762371409803760113409979485030492256710954152453024520019770144	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	80009268962334126920178255804162761688567805629249676099268083468258508907929	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	93136922578138436918954760555298967025117122423743932560723538853798650104824	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	46221454940863290619858136379267924731844484542949574091169797578238219907299	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
Job timed out after * minutes				4 test runs
	chip_sw_exit_test_unlocked_bootstrap	41353859799973662907860891346143161984912982835645967118626021728793160144185	None
	chip_sw_keymgr_dpe_sideload_otbn	11533013288183494028680302721404251225681503601802871556322357135401439569679	None
	ate_bootstrap_one_frame	88872748135782291529049654819282071400719876470847672050254636568352267834432	None
	ate_bootstrap_disjoint	2005015179494157965055269558183535114959387782093322074129368337229167281506	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	114602750535535712591141814729448838455536151571338295366754555554853970304774	438	UVM_INFO @ 19225.822916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	47848191180087710451334933928390395613492027697495587935543355789539910726461	438	UVM_INFO @ 16758.719422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	82581831831979956261611246163244300998557756621124492242723303953597171145518	410	UVM_INFO @ 10052.889547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	26553862859354096521073660238155000746004051908163774138599903396200667502810	359	UVM_INFO @ 2259.432500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	48987222100380506898651993031946115008609377491160427405241188193225194343114	359	UVM_INFO @ 1945.451000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	53539984005329215463460994876138281731185704812310590862687405353774215783986	359	UVM_INFO @ 2176.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				2 test runs
	chip_sw_lc_walkthrough_testunlocks	36669816072630544724477755396930630741831641865945416581538939739992613559871	487	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_core_ibex_icache_invalidate	58992266103331308975960935088682589568857556149496686754235092238270659391979	377	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	78779801403450311743738458523134514825389712596815459054798966906276468726579	379	UVM_INFO @ 2757.443688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	74778966088185240755199607464975340920984839483202712216570739548808582500539	441	UVM_INFO @ 3344.003556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	64417899292983212880776814851602314550178464255079428283972619467338406573329	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	102736467787551131265968786856379569668915940619384730842737780315266789792524	None	Another command (pid=891616) is running. Waiting for it to complete on the server (server_pid=186443)... Another command (pid=681158) is running. Waiting for it to complete on the server (server_pid=186443)... Another command (pid=807756) is running. Waiting for it to complete on the server (server_pid=186443)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	11084311433163531013108450148289872615395005122387179898488558391467098867831	365	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	24992088991649466387880169119735573486829569324656446913378617099749407690232	391	UVM_INFO @ 2747.721828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	114069558595131461816235475997699826562704664042661397407474913912291603654818	337	UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	70528233917279870065891798116763137080064991868384241819317861409355340012931	404	UVM_INFO @ 6572.875599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	87760046971272208977536961745819416781417967981002371485077131696546685357807	380	UVM_ERROR @ 3634.835870 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3634.835870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	chip_sw_lc_ctrl_test_locked0_to_scrap	981008954910120750979043601225742172713350466175953196059410134880660029800	375	UVM_INFO @ 10466.985134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	52551650756122387747211077551736225473491101438458200864734812496506626556312	377	UVM_ERROR @ 3158.444740 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3158.444740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	66067302241199541400563923457626658909972757650577630738144052989323704446071	396	UVM_INFO @ 34710.223714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	63724945132507252656639908225806629911640774150332328545042139660869045088918	371	UVM_INFO @ 2885.913295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	20964288044075167564621999932922498767901732583665654701191882733128257438398	378	UVM_INFO @ 3107.963435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	107333104569537575866026898515332672917605850050575667716015577031469190874651	404	UVM_INFO @ 12010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	19290716953232868983295184664093529927297085234699225325735939727089551274757	400	UVM_INFO @ 9063.529632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	83098614811982086381019458684501393508921620602421006694331955307535211083177	407	UVM_INFO @ 3680.576422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_csr_rw	103251602694273282290367731963843035597258121696348979459688605240686632080319	5365	UVM_INFO @ 2441.473508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	47570335309163963016470515502438176003094728692419828638555897309349519252568	387	UVM_ERROR @ 3167.040120 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 3167.040120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	17519335511431243824386231906570323266266641889762121542577555115431191699855	299	UVM_INFO @ 3619.863250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	100553972155200859663326442660176571320871766245742247222173106888681884988032	391	UVM_INFO @ 8301.197517 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	92474319527114591757409529784713831834421874045504177664068888879399857812382	339	UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_shutdown_output	36418904476009779642434160422053965957542471930074307724712146331706677307245	413	UVM_ERROR @ 25355.487148 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 25355.487148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement				1 test run
	rom_raw_unlock	85325811489454515555638348234640344189432315869672096695340166353308913844384	403	UVM_INFO @ 19028.244723 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---