Simulation Results: csrng

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.77 %
  • code
  • 92.25 %
  • assert
  • 94.10 %
  • func
  • 76.95 %
  • block
  • 96.87 %
  • line
  • 97.70 %
  • branch
  • 92.22 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 94.325us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 0.000s 32.428us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 68.623us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 15.000s 1143.001us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 0.000s 12.546us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 84.028us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 68.623us 1 1 100.00
csrng_csr_aliasing 0.000s 12.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 267.709us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 22.000s 2715.823us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 22.000s 2715.823us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 119.000s 11160.045us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 24.538us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 14.245us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 55.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 55.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 0.000s 32.428us 1 1 100.00
csrng_csr_rw 1.000s 68.623us 1 1 100.00
csrng_csr_aliasing 0.000s 12.546us 1 1 100.00
csrng_same_csr_outstanding 1.000s 42.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 0.000s 32.428us 1 1 100.00
csrng_csr_rw 1.000s 68.623us 1 1 100.00
csrng_csr_aliasing 0.000s 12.546us 1 1 100.00
csrng_same_csr_outstanding 1.000s 42.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
csrng_tl_intg_err 4.000s 224.968us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 1.000s 19.055us 1 1 100.00
csrng_csr_rw 1.000s 68.623us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 267.709us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 119.000s 11160.045us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 267.709us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 119.000s 11160.045us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 267.709us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 224.968us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
csrng_sec_cm 2.000s 98.957us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 476.477us 1 1 100.00
csrng_err 1.000s 97.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 1.000s 7.164us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 29745924852084783036061413900473793659211085907668184996881501864869539659602 115
UVM_INFO @ 7163663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---