Simulation Results: edn/edn0

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.53 %
  • code
  • 82.13 %
  • assert
  • 96.31 %
  • func
  • 81.15 %
  • line
  • 97.83 %
  • branch
  • 92.61 %
  • cond
  • 87.00 %
  • toggle
  • 80.52 %
  • FSM
  • 52.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.740s 46.996us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 52.417us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 78.006us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.640s 668.994us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.750s 63.902us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.820s 84.240us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 78.006us 1 1 100.00
edn_csr_aliasing 0.750s 63.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.140s 113.432us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.140s 113.432us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.140s 113.432us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.680s 43.165us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 29.462us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 27.662us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 12.870us 1 1 100.00
edn_disable_auto_req_mode 1.040s 34.536us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.250s 280.321us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 18.768us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 115.762us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.850s 489.211us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.850s 489.211us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 52.417us 1 1 100.00
edn_csr_rw 0.830s 78.006us 1 1 100.00
edn_csr_aliasing 0.750s 63.902us 1 1 100.00
edn_same_csr_outstanding 1.000s 29.790us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 52.417us 1 1 100.00
edn_csr_rw 0.830s 78.006us 1 1 100.00
edn_csr_aliasing 0.750s 63.902us 1 1 100.00
edn_same_csr_outstanding 1.000s 29.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
edn_tl_intg_err 1.320s 155.488us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 42.681us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 29.462us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 29.462us 1 1 100.00
edn_sec_cm 3.660s 677.953us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 29.462us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.320s 155.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.730s 14271.741us 1 1 100.00