Simulation Results: edn/edn1

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.75 %
  • code
  • 85.34 %
  • assert
  • 98.70 %
  • func
  • 79.20 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 91.08 %
  • toggle
  • 95.70 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.740s 43.266us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.700s 60.828us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 14.849us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.670s 329.371us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.840s 29.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.860s 17.946us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 14.849us 1 1 100.00
edn_csr_aliasing 0.840s 29.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.810s 61.362us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.810s 61.362us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.810s 61.362us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 29.046us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.150s 47.214us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 22.950us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 18.378us 1 1 100.00
edn_disable_auto_req_mode 0.950s 81.250us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.670s 71.420us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.750s 29.687us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.600s 173.386us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.130s 778.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.130s 778.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.700s 60.828us 1 1 100.00
edn_csr_rw 0.720s 14.849us 1 1 100.00
edn_csr_aliasing 0.840s 29.151us 1 1 100.00
edn_same_csr_outstanding 0.910s 100.085us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.700s 60.828us 1 1 100.00
edn_csr_rw 0.720s 14.849us 1 1 100.00
edn_csr_aliasing 0.840s 29.151us 1 1 100.00
edn_same_csr_outstanding 0.910s 100.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
edn_tl_intg_err 0.930s 43.745us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.680s 44.899us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.150s 47.214us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.150s 47.214us 1 1 100.00
edn_sec_cm 1.790s 247.353us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.150s 47.214us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 0.930s 43.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 34.050s 3085.560us 1 1 100.00