Simulation Results: entropy_src/rng_4bits

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.57 %
  • code
  • 88.46 %
  • assert
  • 84.56 %
  • func
  • 53.70 %
  • block
  • 94.43 %
  • line
  • 97.09 %
  • branch
  • 86.75 %
  • toggle
  • 76.25 %
  • FSM
  • 93.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 30.438us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 98.397us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 39.819us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 9.000s 3147.589us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 1.000s 188.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 127.343us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 39.819us 1 1 100.00
entropy_src_csr_aliasing 1.000s 188.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 30.438us 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
entropy_src_fw_ov 201.000s 14019.884us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 201.000s 14019.884us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 270.000s 13083.513us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
entropy_src_intr 9.000s 1567.113us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
entropy_src_functional_alerts 3.000s 353.325us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 41.000s 13774.708us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 349.803us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 13.088us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 20.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 74.480us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 74.480us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 98.397us 1 1 100.00
entropy_src_csr_rw 1.000s 39.819us 1 1 100.00
entropy_src_csr_aliasing 1.000s 188.221us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 165.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 98.397us 1 1 100.00
entropy_src_csr_rw 1.000s 39.819us 1 1 100.00
entropy_src_csr_aliasing 1.000s 188.221us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 165.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 1.000s 74.240us 1 1 100.00
entropy_src_tl_intg_err 3.000s 305.702us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
entropy_src_cfg_regwen 2.000s 121.685us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
entropy_src_fw_ov 201.000s 14019.884us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
entropy_src_sec_cm 1.000s 74.240us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
entropy_src_sec_cm 1.000s 74.240us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 36.000s 13055.747us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
entropy_src_sec_cm 1.000s 74.240us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
entropy_src_sec_cm 1.000s 74.240us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 47.003us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 3.000s 353.325us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 305.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 43.000s 13072.382us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 1.000s 14.715us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 110909650009681263234269365165328745986059840246501957570943102200653085763259 114
UVM_INFO @ 14714537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---