Simulation Results: hmac

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 76.06 %
  • code
  • 86.90 %
  • assert
  • 97.60 %
  • func
  • 43.69 %
  • line
  • 99.64 %
  • branch
  • 98.86 %
  • cond
  • 95.69 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.110s 3631.379us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 107.701us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.720s 53.812us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.870s 322.569us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 0.820s 42.409us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.720s 29.888us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.720s 53.812us 1 1 100.00
hmac_csr_aliasing 0.820s 42.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 3.930s 857.787us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 45.640s 6861.317us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 142.490s 40738.387us 1 1 100.00
hmac_test_sha384_vectors 325.340s 71324.020us 1 1 100.00
hmac_test_sha512_vectors 16.510s 1409.472us 1 1 100.00
hmac_test_hmac256_vectors 7.840s 1725.471us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 714.782us 1 1 100.00
hmac_test_hmac512_vectors 8.460s 350.992us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.620s 9664.189us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 530.340s 28863.116us 1 1 100.00
error 1 1 100.00
hmac_error 47.080s 13533.624us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 81.570s 23677.777us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.110s 3631.379us 1 1 100.00
hmac_long_msg 3.930s 857.787us 1 1 100.00
hmac_back_pressure 45.640s 6861.317us 1 1 100.00
hmac_datapath_stress 530.340s 28863.116us 1 1 100.00
hmac_burst_wr 13.620s 9664.189us 1 1 100.00
hmac_stress_all 240.100s 9502.846us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.110s 3631.379us 1 1 100.00
hmac_long_msg 3.930s 857.787us 1 1 100.00
hmac_back_pressure 45.640s 6861.317us 1 1 100.00
hmac_datapath_stress 530.340s 28863.116us 1 1 100.00
hmac_wipe_secret 81.570s 23677.777us 1 1 100.00
hmac_test_sha256_vectors 142.490s 40738.387us 1 1 100.00
hmac_test_sha384_vectors 325.340s 71324.020us 1 1 100.00
hmac_test_sha512_vectors 16.510s 1409.472us 1 1 100.00
hmac_test_hmac256_vectors 7.840s 1725.471us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 714.782us 1 1 100.00
hmac_test_hmac512_vectors 8.460s 350.992us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.110s 3631.379us 1 1 100.00
hmac_long_msg 3.930s 857.787us 1 1 100.00
hmac_back_pressure 45.640s 6861.317us 1 1 100.00
hmac_datapath_stress 530.340s 28863.116us 1 1 100.00
hmac_burst_wr 13.620s 9664.189us 1 1 100.00
hmac_error 47.080s 13533.624us 1 1 100.00
hmac_wipe_secret 81.570s 23677.777us 1 1 100.00
hmac_test_sha256_vectors 142.490s 40738.387us 1 1 100.00
hmac_test_sha384_vectors 325.340s 71324.020us 1 1 100.00
hmac_test_sha512_vectors 16.510s 1409.472us 1 1 100.00
hmac_test_hmac256_vectors 7.840s 1725.471us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 714.782us 1 1 100.00
hmac_test_hmac512_vectors 8.460s 350.992us 1 1 100.00
hmac_stress_all 240.100s 9502.846us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 240.100s 9502.846us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.540s 41.360us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.540s 40.806us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.920s 3625.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.920s 3625.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 107.701us 1 1 100.00
hmac_csr_rw 0.720s 53.812us 1 1 100.00
hmac_csr_aliasing 0.820s 42.409us 1 1 100.00
hmac_same_csr_outstanding 2.020s 134.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 107.701us 1 1 100.00
hmac_csr_rw 0.720s 53.812us 1 1 100.00
hmac_csr_aliasing 0.820s 42.409us 1 1 100.00
hmac_same_csr_outstanding 2.020s 134.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 71.989us 1 1 100.00
hmac_tl_intg_err 1.350s 883.961us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.350s 883.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.110s 3631.379us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.300s 53.155us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 170.820s 15228.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.380s 184.837us 1 1 100.00