Simulation Results: i2c

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.79 %
  • code
  • 78.57 %
  • assert
  • 96.62 %
  • func
  • 79.18 %
  • line
  • 96.72 %
  • branch
  • 92.55 %
  • cond
  • 84.89 %
  • toggle
  • 74.04 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 9.530s 4634.447us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.140s 3484.944us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.630s 29.807us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.620s 343.038us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.450s 591.568us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.700s 30.046us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.830s 207.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.620s 343.038us 1 1 100.00
i2c_csr_aliasing 0.700s 30.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.810s 152.258us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 134.400s 26571.704us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 114.600s 4971.995us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.620s 42.471us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 49.320s 5555.607us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 18.330s 1529.483us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.780s 118.936us 1 1 100.00
i2c_host_fifo_fmt_empty 2.380s 1575.334us 1 1 100.00
i2c_host_fifo_reset_rx 4.630s 805.200us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 35.540s 14722.769us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.040s 1565.114us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.080s 325.754us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.210s 896.018us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 303.100s 44865.707us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 2.020s 2036.783us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 49.380s 3673.337us 1 1 100.00
i2c_target_intr_smoke 3.090s 4003.404us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.920s 279.018us 1 1 100.00
i2c_target_fifo_reset_tx 0.750s 165.333us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 389.700s 53337.963us 1 1 100.00
i2c_target_stress_rd 49.380s 3673.337us 1 1 100.00
i2c_target_intr_stress_wr 7.980s 7730.078us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 3.720s 2504.252us 1 1 100.00
target_clock_stretch 0 1 0.00
i2c_target_stretch 8.690s 10002.620us 0 1 0.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.280s 2452.241us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.840s 692.478us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.320s 873.966us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.740s 131.269us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 114.600s 4971.995us 1 1 100.00
i2c_host_perf_precise 37.110s 6171.426us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.040s 1565.114us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 0.920s 51.494us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.460s 2290.155us 1 1 100.00
i2c_target_nack_acqfull_addr 1.250s 510.853us 1 1 100.00
i2c_target_nack_txstretch 0.820s 191.318us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.460s 509.091us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.050s 762.443us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.550s 28.043us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.640s 18.389us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 0.930s 217.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 0.930s 217.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.630s 29.807us 1 1 100.00
i2c_csr_rw 0.620s 343.038us 1 1 100.00
i2c_csr_aliasing 0.700s 30.046us 1 1 100.00
i2c_same_csr_outstanding 0.720s 42.177us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.630s 29.807us 1 1 100.00
i2c_csr_rw 0.620s 343.038us 1 1 100.00
i2c_csr_aliasing 0.700s 30.046us 1 1 100.00
i2c_same_csr_outstanding 0.720s 42.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 0.900s 348.248us 1 1 100.00
i2c_sec_cm 0.750s 56.070us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 0.900s 348.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 4.320s 338.092us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.810s 124.654us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.990s 143.328us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 32766249358897201171243107192679164950260623034874639167003433993716165378424 94
UVM_INFO @ 152257638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 61425263962229726612911498850392875359643472076498014649955481101627469937383 137
UVM_INFO @ 26571703696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 72577768268939841422176491773885158774557714176559944617537866373224757392067 92
UVM_INFO @ 143328389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 17638065365791286248568699128009344858962312429794514410230430850998606889639 90
UVM_INFO @ 896018252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! 1 test run
i2c_target_stretch 113721250678585148569719153580401353576378281201046566855492275446241887937416 84
UVM_INFO @ 10002619971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 45830585714255821792277742063884203912213456372987172274703665532682756859346 84
UVM_INFO @ 124654302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1251) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! 1 test run
i2c_target_stress_all 13268754401637443142639428331946898680752868618595294117411837155017021103736 99
UVM_INFO @ 44865707225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 2216851594644014607867287209526858520236441571840094246202350386072571509485 90
UVM_INFO @ 338091654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 45006772571644437161901319406420001527412562279721006525473054807070567023430 84
UVM_INFO @ 191317906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---