Simulation Results: keymgr_dpe/earlgrey

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.03 %
  • code
  • 82.37 %
  • assert
  • 97.67 %
  • func
  • 15.05 %
  • line
  • 97.27 %
  • branch
  • 93.67 %
  • cond
  • 86.00 %
  • toggle
  • 59.22 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 6.820s 224.051us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.590s 19.411us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.750s 14.320us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 4.270s 921.179us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 80.130us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 0.800s 143.813us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.750s 14.320us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 80.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.630s 38.368us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.680s 23.816us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 1.360s 25.099us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 1.360s 25.099us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.590s 19.411us 1 1 100.00
keymgr_dpe_csr_rw 0.750s 14.320us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 80.130us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.880s 79.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.590s 19.411us 1 1 100.00
keymgr_dpe_csr_rw 0.750s 14.320us 1 1 100.00
keymgr_dpe_csr_aliasing 1.270s 80.130us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.880s 79.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 9.170s 2986.555us 1 1 100.00
keymgr_dpe_tl_intg_err 2.120s 491.375us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 2.432us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 2.432us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 2.432us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 2.432us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.070s 41.238us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 9.170s 2986.555us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 9.170s 2986.555us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 58546615361372308309481568624747758411204054137979137047890974983920852878396 83
UVM_ERROR @ 2432236 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 2432236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 107010486586653403601697636407520044914173174658030200590455408511331675572057 83
UVM_ERROR @ 41238406 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 41238406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---