Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.80 %
  • code
  • 83.97 %
  • assert
  • 94.69 %
  • func
  • 93.73 %
  • line
  • 97.11 %
  • branch
  • 93.61 %
  • cond
  • 79.24 %
  • toggle
  • 85.42 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.780s 23.812us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.570s 46.888us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.720s 47.651us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.910s 520.508us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.700s 260.038us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 32.808us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.720s 47.651us 1 1 100.00
lc_ctrl_csr_aliasing 0.700s 260.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.410s 89.363us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.100s 1386.090us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.570s 36.639us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.750s 108.134us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.100s 332.352us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_prog_failure 1.750s 108.134us 1 1 100.00
lc_ctrl_errors 3.100s 332.352us 1 1 100.00
lc_ctrl_security_escalation 2.940s 2257.046us 1 1 100.00
lc_ctrl_jtag_state_failure 13.220s 2545.358us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.820s 369.031us 0 1 0.00
lc_ctrl_jtag_errors 13.380s 1846.174us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 1.260s 183.070us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.240s 1272.488us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.820s 369.031us 0 1 0.00
lc_ctrl_jtag_errors 13.380s 1846.174us 1 1 100.00
lc_ctrl_jtag_access 3.370s 8224.997us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 5.690s 8556.963us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.700s 41.464us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.960s 795.523us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.500s 2936.155us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.090s 516.707us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.930s 172.386us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.100s 635.065us 1 1 100.00
lc_ctrl_jtag_alert_test 1.050s 94.575us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.250s 517.654us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.590s 16.887us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 5.020s 490.070us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.780s 65.324us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.050s 33.563us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.050s 33.563us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 46.888us 1 1 100.00
lc_ctrl_csr_rw 0.720s 47.651us 1 1 100.00
lc_ctrl_csr_aliasing 0.700s 260.038us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 41.091us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 46.888us 1 1 100.00
lc_ctrl_csr_rw 0.720s 47.651us 1 1 100.00
lc_ctrl_csr_aliasing 0.700s 260.038us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 41.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
lc_ctrl_tl_intg_err 0.860s 66.472us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.860s 66.472us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.100s 1386.090us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.370s 655.889us 1 1 100.00
lc_ctrl_sec_cm 4.010s 133.416us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.940s 2257.046us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.410s 89.363us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.240s 1272.488us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.220s 973.783us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.220s 973.783us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.330s 1549.461us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.280s 1611.398us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.280s 1611.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 25.400s 1965.338us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 91389926847471680963496716986664601137970192756769973408015854296645569019302 338
UVM_INFO @ 369031163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 109901861341598234533444132091977881451685695589003564057813717042725625765429 1146
UVM_INFO @ 1965337665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---