Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.29 %
  • code
  • 83.74 %
  • assert
  • 94.83 %
  • func
  • 92.29 %
  • line
  • 97.09 %
  • branch
  • 93.43 %
  • cond
  • 79.01 %
  • toggle
  • 84.68 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
93.33%
V2S
90.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.870s 45.056us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.570s 17.818us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.500s 28.630us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.730s 78.847us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.610s 64.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.660s 19.231us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.500s 28.630us 1 1 100.00
lc_ctrl_csr_aliasing 0.610s 64.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.210s 233.720us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 3317.371us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.460s 40.714us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.200s 95.319us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.550s 379.294us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_prog_failure 1.200s 95.319us 1 1 100.00
lc_ctrl_errors 3.550s 379.294us 1 1 100.00
lc_ctrl_security_escalation 3.840s 441.422us 1 1 100.00
lc_ctrl_jtag_state_failure 5.290s 362.395us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.470s 1308.743us 1 1 100.00
lc_ctrl_jtag_errors 10.840s 5677.283us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 1.230s 149.968us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.110s 2552.911us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.470s 1308.743us 1 1 100.00
lc_ctrl_jtag_errors 10.840s 5677.283us 1 1 100.00
lc_ctrl_jtag_access 3.330s 625.101us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.060s 4099.168us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.650s 168.306us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.720s 75.910us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 2.420s 3439.375us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.180s 860.861us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.660s 76.535us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.400s 349.117us 1 1 100.00
lc_ctrl_jtag_alert_test 0.570s 36.837us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.610s 579.233us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.490s 53.031us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.910s 21348.769us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.570s 64.232us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.150s 301.679us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.150s 301.679us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 17.818us 1 1 100.00
lc_ctrl_csr_rw 0.500s 28.630us 1 1 100.00
lc_ctrl_csr_aliasing 0.610s 64.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.580s 19.376us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 17.818us 1 1 100.00
lc_ctrl_csr_rw 0.500s 28.630us 1 1 100.00
lc_ctrl_csr_aliasing 0.610s 64.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.580s 19.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
lc_ctrl_tl_intg_err 1.060s 170.990us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.060s 170.990us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 3317.371us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.730s 2357.160us 1 1 100.00
lc_ctrl_sec_cm 3.570s 206.524us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.840s 441.422us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.210s 233.720us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.110s 2552.911us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.710s 247.516us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.710s 247.516us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.050s 536.023us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.400s 697.790us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.400s 697.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 14.480s 7925.398us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 70531998122998047272009060724909793586350112573549747196210838881896476773088 773
UVM_INFO @ 362394861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 52847775022974890653115202885476265456689477130020660376608890254181498876090 588
UVM_INFO @ 2552910644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 55247229618414271653403466929371252349742168017466154666797877680946201249640 3628
UVM_INFO @ 7925398300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---