Simulation Results: otp_ctrl

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.34 %
  • code
  • 77.42 %
  • assert
  • 94.38 %
  • func
  • 72.23 %
  • line
  • 88.55 %
  • branch
  • 83.32 %
  • cond
  • 90.22 %
  • toggle
  • 81.10 %
  • FSM
  • 43.92 %
Validation stages
V1
88.89%
V2
95.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 0.770s 59.928us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.760s 954.816us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 0.830s 172.194us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.970s 9426.696us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 1.550s 840.492us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 0.640s 28.766us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 0.830s 172.194us 1 1 100.00
otp_ctrl_csr_aliasing 1.550s 840.492us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 0.700s 468.300us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 0.700s 139.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 10.670s 3765.629us 1 1 100.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.290s 324.738us 0 1 0.00
partition_check 2 2 100.00
otp_ctrl_background_chks 6.200s 948.606us 1 1 100.00
otp_ctrl_check_fail 16.460s 2055.064us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 1.610s 262.503us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 1.690s 1678.466us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.710s 2065.883us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 5.030s 493.562us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 3.330s 2130.998us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 4.840s 279.655us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 101.500s 24301.989us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 0.680s 42.058us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 0.990s 99.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.400s 204.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.400s 204.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.760s 954.816us 1 1 100.00
otp_ctrl_csr_rw 0.830s 172.194us 1 1 100.00
otp_ctrl_csr_aliasing 1.550s 840.492us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.590s 2121.055us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.760s 954.816us 1 1 100.00
otp_ctrl_csr_rw 0.830s 172.194us 1 1 100.00
otp_ctrl_csr_aliasing 1.550s 840.492us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.590s 2121.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
otp_ctrl_tl_intg_err 1.040s 318.584us 0 1 0.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
otp_ctrl_tl_intg_err 1.040s 318.584us 0 1 0.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_macro_errs 3.330s 2130.998us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_macro_errs 3.330s 2130.998us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.720s 621.812us 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.290s 324.738us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 16.460s 2055.064us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.230s 1373.783us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 72.830s 18693.206us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 1.610s 262.503us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.650s 420.483us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 3.330s 2130.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 15.880s 8747.807us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 46.140s 8151.513us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_init_fail 105785871715408972170464318119153990491473732346000402579908062056086707075684 1654
UVM_INFO @ 324738045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_stress_all_with_rand_reset 64501536011395035319276835577364469424950858331234636766670873476497713105513 47043
UVM_INFO @ 8151513455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_tl_intg_err 1021518336433266607538244302875963958762285073860086076915028370941085790717 120
UVM_INFO @ 318584143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 59082606224758409452849062248344143905142894700907868294502666020762018974112 103
UVM_INFO @ 28765974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---