Simulation Results: pwrmgr

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 94.46 %
  • assert
  • 97.39 %
  • func
  • 96.05 %
  • line
  • 98.93 %
  • branch
  • 95.43 %
  • cond
  • 93.92 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
72.73%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.350s 29.732us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.330s 24.065us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.010s 183.288us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.350s 18.104us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.380s 48.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 18.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.410s 94.918us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.410s 94.918us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.530s 55.918us 1 1 100.00
pwrmgr_lowpower_invalid 0.350s 79.054us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.390s 82.072us 1 1 100.00
pwrmgr_reset_invalid 0.520s 112.618us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.390s 82.072us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.320s 55.600us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.430s 157.743us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.520s 99.403us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.023s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.320s 181.591us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.600s 27.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.600s 27.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.330s 24.065us 1 1 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 18.104us 1 1 100.00
pwrmgr_same_csr_outstanding 0.430s 24.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.330s 24.065us 1 1 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 18.104us 1 1 100.00
pwrmgr_same_csr_outstanding 0.430s 24.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.018s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.018s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.060s 1868.969us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.320s 55.600us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.430s 797.182us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.460s 97.736us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.320s 39.659us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.022s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.340s 36.869us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.023s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.550s 364.139us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.340s 37.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.410s 356.645us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.020s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
pwrmgr_glitch 24072980056555585890764600681630970653226639322930859372615032315836526382480 None
pwrmgr_tl_intg_err 111482101714911839500486233711286671317399052903280382238300668232246005431681 None
pwrmgr_sec_cm 58046361233816766069975464400091611868908205424449804191314882534444575520529 None
pwrmgr_stress_all_with_rand_reset 87518289158714130631402867004614589072429002542697647636968209491008139659747 None
pwrmgr_stress_all 114209257860276153812297148859955238662138746480485650336738024676195411701532 None
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 42277352318273046006228063187436481925113563546241133078377802003462998482167 85
UVM_ERROR @ 356644648 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356644648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---