Simulation Results: rom_ctrl/192kb

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.59 %
  • code
  • 92.69 %
  • assert
  • 97.68 %
  • func
  • 84.41 %
  • line
  • 98.82 %
  • branch
  • 98.19 %
  • cond
  • 98.07 %
  • toggle
  • 95.02 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.310s 4178.975us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.430s 81.218us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.040s 169.752us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.390s 293.437us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.510s 52.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.270s 53.228us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.040s 169.752us 1 1 100.00
rom_ctrl_csr_aliasing 4.510s 52.817us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.060s 95.248us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.050s 65.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.800s 3933.608us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 40.810s 14645.005us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.036s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.050s 128.977us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.100s 1063.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.100s 1063.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.430s 81.218us 1 1 100.00
rom_ctrl_csr_rw 4.040s 169.752us 1 1 100.00
rom_ctrl_csr_aliasing 4.510s 52.817us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.900s 149.856us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.430s 81.218us 1 1 100.00
rom_ctrl_csr_rw 4.040s 169.752us 1 1 100.00
rom_ctrl_csr_aliasing 4.510s 52.817us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.900s 149.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.390s 239.104us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
rom_ctrl_tl_intg_err 146.040s 249.492us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.310s 4178.975us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.310s 4178.975us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.310s 4178.975us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 146.040s 249.492us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
rom_ctrl_kmac_err_chk 3600.036s 0.000us 0 1 0.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.640s 14809.636us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.390s 239.104us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 362.880s 2624.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 7.480s 413.793us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 54468543463850285725323409736762126048543659802787549774656123995080744128214 85
UVM_INFO @ 3933608294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_kmac_err_chk 29404856602726716488619931139787073220174176593885751265831022770690997534924 None
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 28744932144732139749776547278777367247348480085081982113441782873832499597669 87
UVM_INFO @ 413792681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---