Simulation Results: rstmgr

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.30 %
  • code
  • 98.99 %
  • assert
  • 98.39 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 98.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 0.830s 277.453us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.420s 93.492us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 1.810s 376.452us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.430s 69.480us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.700s 128.031us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00
rstmgr_csr_aliasing 0.430s 69.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.500s 230.823us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 661.962us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.390s 71.283us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.810s 1268.589us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.810s 1268.589us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.810s 1268.589us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.810s 1268.589us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 8.220s 4419.530us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.430s 72.238us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 0.680s 103.956us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 0.680s 103.956us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.420s 93.492us 1 1 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00
rstmgr_csr_aliasing 0.430s 69.480us 1 1 100.00
rstmgr_same_csr_outstanding 0.670s 139.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.420s 93.492us 1 1 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00
rstmgr_csr_aliasing 0.430s 69.480us 1 1 100.00
rstmgr_same_csr_outstanding 0.670s 139.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.660s 16871.874us 1 1 100.00
rstmgr_tl_intg_err 0.880s 433.901us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.660s 16871.874us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.660s 16871.874us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 0.880s 433.901us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.660s 195.028us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.190s 1406.418us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.570s 304.406us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.660s 16871.874us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.420s 69.112us 1 1 100.00