Simulation Results: rv_timer

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.21 %
  • code
  • 94.66 %
  • assert
  • 98.09 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.500s 110.919us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.300s 30.285us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.290s 45.871us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.280s 314.877us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.300s 35.887us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.370s 27.627us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.290s 45.871us 1 1 100.00
rv_timer_csr_aliasing 0.300s 35.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.480s 281.788us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.980s 2448.834us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.310s 119.938us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.310s 119.938us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.100s 2997.926us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.280s 30.793us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.320s 18.657us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.730s 25.939us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.730s 25.939us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.300s 30.285us 1 1 100.00
rv_timer_csr_rw 0.290s 45.871us 1 1 100.00
rv_timer_csr_aliasing 0.300s 35.887us 1 1 100.00
rv_timer_same_csr_outstanding 0.400s 30.283us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.300s 30.285us 1 1 100.00
rv_timer_csr_rw 0.290s 45.871us 1 1 100.00
rv_timer_csr_aliasing 0.300s 35.887us 1 1 100.00
rv_timer_same_csr_outstanding 0.400s 30.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.400s 161.771us 1 1 100.00
rv_timer_tl_intg_err 0.520s 238.303us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.520s 238.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.340s 1835.881us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.300s 48.642us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 12.200s 3000.744us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 71406146949994751013972844488875297215941437299824414905910450908549082908775 83
UVM_INFO @ 1835881064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 64094898209084212278446309139860442828779171824941469698821001237606238279938 81
UVM_INFO @ 48641593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---