Simulation Results: spi_device/1r1w

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.66 %
  • code
  • 90.91 %
  • assert
  • 95.40 %
  • func
  • 64.68 %
  • line
  • 98.84 %
  • branch
  • 98.08 %
  • cond
  • 96.08 %
  • toggle
  • 74.30 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 41.080s 28700.943us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.580s 40.040us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.310s 508.089us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 13.580s 1410.818us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.260s 91.236us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.890s 292.825us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.310s 508.089us 1 1 100.00
spi_device_csr_aliasing 1.260s 91.236us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.360s 69.267us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.540s 32.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.410s 82.804us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.370s 2.732us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.360s 3.674us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.580s 42.022us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.580s 42.022us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.370s 23.958us 1 1 100.00
spi_device_tpm_sts_read 0.430s 455.468us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.680s 2968.004us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.360s 2647.354us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.570s 10399.524us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.570s 10399.524us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.430s 154.067us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.430s 154.067us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.430s 154.067us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.430s 154.067us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.430s 154.067us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.570s 4335.160us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 10.420s 2718.452us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 10.420s 2718.452us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 10.420s 2718.452us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.430s 117.660us 1 1 100.00
spi_device_read_buffer_direct 5.070s 1687.208us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 10.420s 2718.452us 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 194.100s 505144.894us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 0.890s 34.005us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 0.890s 34.005us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 14.520s 3709.889us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 41.080s 28700.943us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 19.280s 8412.453us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 7.990s 923.407us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.390s 113.477us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.400s 12.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.490s 759.777us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.490s 759.777us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.580s 40.040us 1 1 100.00
spi_device_csr_rw 1.310s 508.089us 1 1 100.00
spi_device_csr_aliasing 1.260s 91.236us 1 1 100.00
spi_device_same_csr_outstanding 1.840s 570.725us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.580s 40.040us 1 1 100.00
spi_device_csr_rw 1.310s 508.089us 1 1 100.00
spi_device_csr_aliasing 1.260s 91.236us 1 1 100.00
spi_device_same_csr_outstanding 1.840s 570.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.570s 198.682us 1 1 100.00
spi_device_tl_intg_err 8.620s 648.342us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.620s 648.342us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 55067564375682153296205240435246735141984826883370207638174472521708419992680 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2073711 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2073711 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 104663211594642863933954100921406728576387708688932219102978325631397105143677 76
UVM_ERROR @ 1053376 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x199 [110011001] vs 0x0 [0])
UVM_ERROR @ 1107376 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12a [100101010] vs 0x0 [0])
UVM_ERROR @ 1172376 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e [11110] vs 0x0 [0])
UVM_ERROR @ 1184376 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x122 [100100010] vs 0x0 [0])