Simulation Results: spi_host

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.83 %
  • code
  • 91.25 %
  • assert
  • 96.41 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 72.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 375.566us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 5.000s 30.395us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 5.000s 54.453us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 6.000s 945.209us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 5.000s 17.178us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 5.000s 40.442us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 5.000s 54.453us 1 1 100.00
spi_host_csr_aliasing 5.000s 17.178us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 4.000s 18.126us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 4.000s 58.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 0.000s 54.779us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 66.896us 1 1 100.00
spi_host_error_cmd 5.000s 19.828us 1 1 100.00
spi_host_event 7.000s 1022.067us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 175.310us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 175.310us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 175.310us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 154.000s 26396.936us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 33.000s 2048.737us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 4.000s 26.834us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 175.310us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 175.310us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 375.566us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 375.566us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 68.364us 1 1 100.00
spien 1 1 100.00
spi_host_spien 1.000s 230.683us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 508.000s 97532.951us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 5.000s 357.831us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 66.896us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 5.000s 17.522us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 4.000s 34.452us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 356.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 356.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 5.000s 30.395us 1 1 100.00
spi_host_csr_rw 5.000s 54.453us 1 1 100.00
spi_host_csr_aliasing 5.000s 17.178us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.267us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 5.000s 30.395us 1 1 100.00
spi_host_csr_rw 5.000s 54.453us 1 1 100.00
spi_host_csr_aliasing 5.000s 17.178us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 0.000s 726.410us 1 1 100.00
spi_host_sec_cm 1.000s 75.622us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 0.000s 726.410us 1 1 100.00