Simulation Results: sram_ctrl/main

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.38 %
  • code
  • 95.07 %
  • assert
  • 97.28 %
  • func
  • 90.80 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 705.893us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 27.101us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.166us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 223.256us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 40.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 693.302us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 35.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 40.400us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 168.000s 12572.585us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 45.000s 22781.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 2830.353us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 119.000s 20935.188us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 111.000s 8897.322us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 5.000s 1373.147us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 17.000s 30178.865us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 3008.672us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 4999.441us 1 1 100.00
sram_ctrl_partial_access_b2b 77.000s 13320.279us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 999.375us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 3724.171us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 719.281us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 495.110us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 355.468us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 705.893us 1 1 100.00
sram_ctrl_partial_access 3.000s 4999.441us 1 1 100.00
sram_ctrl_access_during_key_req 5.000s 1373.147us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 199.000s 55712.318us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 156.187us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 156.187us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.101us 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 40.400us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.101us 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 40.400us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 9.000s 7673.363us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 283.068us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 283.068us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 495.110us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 495.110us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.166us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 3008.672us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 3008.672us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 3008.672us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 17.000s 30178.865us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 9.000s 7673.363us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 705.893us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 705.893us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 3008.672us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 17.000s 30178.865us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 705.893us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 672.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 9168.227us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 113382327681673037997249484133331334832660983835959346150407225143096374662685 None
sram_ctrl_mubi_enc_err 16345179477108500674549846626980092446344880121610751812144313132886923603911 None