Simulation Results: sram_ctrl/ret

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.30 %
  • code
  • 81.65 %
  • assert
  • 97.26 %
  • func
  • 95.00 %
  • block
  • 92.05 %
  • line
  • 93.71 %
  • branch
  • 87.91 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 211.739us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.000s 31.764us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.000s 28.322us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 447.665us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 22.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.000s 25.916us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.000s 28.322us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 22.903us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 1803.261us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 121.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 512.912us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 94.000s 4507.004us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 628.082us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 2231.134us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 537.586us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 1285.095us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 86.904us 1 1 100.00
sram_ctrl_partial_access_b2b 222.000s 152381.120us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 127.180us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 36.238us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 40.749us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3162.391us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 49.805us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 211.739us 1 1 100.00
sram_ctrl_partial_access 1.000s 86.904us 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 2231.134us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 28.000s 2631.313us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 45.948us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 928.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 928.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.000s 31.764us 1 1 100.00
sram_ctrl_csr_rw 0.000s 28.322us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 22.903us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 19.586us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.000s 31.764us 1 1 100.00
sram_ctrl_csr_rw 0.000s 28.322us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 22.903us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 19.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 224.516us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 412.144us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 412.144us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3162.391us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3162.391us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.000s 28.322us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1285.095us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1285.095us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1285.095us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 537.586us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 224.516us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 211.739us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 211.739us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 1285.095us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 537.586us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 211.739us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 352.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 1988.887us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 57485519761664779721491370388696774855788580369565537088527091946525728914926 None
sram_ctrl_mubi_enc_err 22900194755086764045086673056735517926892384876237377853444018389808609140184 None