Simulation Results: sysrst_ctrl

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.43 %
  • code
  • 93.70 %
  • assert
  • 95.55 %
  • func
  • 64.04 %
  • line
  • 97.82 %
  • branch
  • 97.70 %
  • cond
  • 95.41 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 0.940s 2134.325us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.040s 2473.768us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.710s 2405.081us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 0.840s 2593.235us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.460s 4043.775us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 0.650s 2120.691us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 2.370s 3696.192us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 0.940s 2181.155us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.640s 2036.615us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 0.650s 2120.691us 1 1 100.00
sysrst_ctrl_csr_aliasing 0.940s 2181.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 163.800s 149446.755us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 23.050s 63166.287us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.270s 3733.150us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.900s 2426.081us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.220s 2509.923us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 0.450s 2365.278us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.560s 2950.904us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.120s 2610.479us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 0.700s 2965.871us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 42.190s 39033.467us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 8.400s 13014.996us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.900s 2027.324us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 0.940s 2025.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.060s 2086.294us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.060s 2086.294us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.460s 4043.775us 1 1 100.00
sysrst_ctrl_csr_rw 0.650s 2120.691us 1 1 100.00
sysrst_ctrl_csr_aliasing 0.940s 2181.155us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 0.870s 5045.860us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.460s 4043.775us 1 1 100.00
sysrst_ctrl_csr_rw 0.650s 2120.691us 1 1 100.00
sysrst_ctrl_csr_aliasing 0.940s 2181.155us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 0.870s 5045.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 23.260s 22011.365us 1 1 100.00
sysrst_ctrl_tl_intg_err 6.750s 22507.926us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 6.750s 22507.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.290s 3530.858us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
sysrst_ctrl_ultra_low_pwr 60379566297881986951764499076207878446553171475879834099256992177259114609620 661
UVM_ERROR @ 2965871457 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2965871457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---