Simulation Results: uart

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.55 %
  • code
  • 90.79 %
  • assert
  • 98.27 %
  • func
  • 55.59 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.12 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 6.050s 6234.484us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.330s 32.986us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.320s 45.709us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 0.820s 636.317us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.320s 14.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.460s 35.463us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.320s 45.709us 1 1 100.00
uart_csr_aliasing 0.320s 14.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 84.950s 137487.114us 1 1 100.00
parity 2 2 100.00
uart_smoke 6.050s 6234.484us 1 1 100.00
uart_tx_rx 84.950s 137487.114us 1 1 100.00
parity_error 2 2 100.00
uart_intr 2.470s 11498.067us 1 1 100.00
uart_rx_parity_err 100.760s 95795.116us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 84.950s 137487.114us 1 1 100.00
uart_intr 2.470s 11498.067us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 65.630s 120093.704us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 24.780s 35921.286us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 12.810s 28192.809us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 2.470s 11498.067us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 2.470s 11498.067us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 2.470s 11498.067us 1 1 100.00
perf 1 1 100.00
uart_perf 9.080s 9546.572us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.900s 10125.016us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.900s 10125.016us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.320s 19232.183us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.330s 4068.469us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 7.040s 7953.696us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.360s 2734.038us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 237.630s 308756.244us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 11.920s 52247.077us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.310s 73.445us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.330s 13.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.750s 425.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.750s 425.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.330s 32.986us 1 1 100.00
uart_csr_rw 0.320s 45.709us 1 1 100.00
uart_csr_aliasing 0.320s 14.243us 1 1 100.00
uart_same_csr_outstanding 0.400s 52.500us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.330s 32.986us 1 1 100.00
uart_csr_rw 0.320s 45.709us 1 1 100.00
uart_csr_aliasing 0.320s 14.243us 1 1 100.00
uart_same_csr_outstanding 0.400s 52.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.420s 913.564us 1 1 100.00
uart_tl_intg_err 0.600s 139.710us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.600s 139.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.440s 12399.112us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 44138226090036359542707659820063105503519895419776782188029799572662135420264 88
UVM_ERROR @ 18949829976 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 18949920885 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (35 [0x23] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 19129072221 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 19129092423 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty