Simulation Results: ac_range_check

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.33%
V2
96.78%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 50.000s 0.000us 18 20 90.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 79.000s 0.000us 20 20 100.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 57.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 0.000us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 0.000us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 40.000s 0.000us 1 1 100.00
stress_all 40 50 80.00
ac_range_check_stress_all 285.000s 0.000us 40 50 80.00
alert_test 50 50 100.00
ac_range_check_alert_test 3.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 0.000us 5 5 100.00
ac_range_check_csr_rw 3.000s 0.000us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 0.000us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 0.000us 5 5 100.00
ac_range_check_csr_rw 3.000s 0.000us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 0.000us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 123.000s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 0.000us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 377.000s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 51.000s 0.000us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke 96935279974159489348513789165832532119026581371251934745236015809797200727821 4248
UVM_ERROR @ 426621605 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 426621605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 14130329095303811579982751187611414335611745896363185845681300891751389344901 4558
UVM_ERROR @ 1360467709 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1360467709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 23808160746524267228115040491391693191350094486673943060165981869247043556090 4327
UVM_ERROR @ 2566131081 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2566131081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 21608363767693307112413235456642046150572102603516504130947445625438511501091 8408
UVM_ERROR @ 1275656554 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1275656554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 12066627093581069073255061843355162004196278294325112579579740165628563221458 18850
UVM_ERROR @ 15181826894 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 15181826894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 104819644569028240297459743806798611918594723213082236878826377484179947176536 14145
UVM_ERROR @ 6448756718 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6448756718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 72948962932788910457224485596365474537292582858358468737594494106059016090954 17176
UVM_ERROR @ 41367273519 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 41367273519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 1401955186953000540133820950037640660078603461048469202734700032577713785444 24127
UVM_ERROR @ 6634785725 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6634785725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 40700879017511781979548983933043243041822743736379696188396821130380182467671 12773
UVM_ERROR @ 4047749469 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 4047749469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 68354874733725457387826443410836885443204996396654686626413322004596560155476 4177
UVM_ERROR @ 14605589673 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 14605589673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 34788549991959559361439110075638422461897895704532999357218463673780654707209 12543
UVM_ERROR @ 17077824513 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 17077824513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
ac_range_check_stress_all 44143384187277211780593553744781849481907133637084969162028972162011245917026 14415
UVM_ERROR @ 100552518889 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
UVM_INFO @ 100552518889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---