Simulation Results: aes/masked

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.23 %
  • code
  • 98.16 %
  • assert
  • 98.57 %
  • func
  • 94.95 %
  • block
  • 98.24 %
  • line
  • 99.43 %
  • branch
  • 95.10 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.79%
V2S
97.58%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 0.000us 1 1 100.00
smoke 50 50 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 4.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 3.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 56.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
key_length 150 150 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 56.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
back2back 100 100 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_b2b 35.000s 0.000us 50 50 100.00
backpressure 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 56.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
failure_test 149 150 99.33
aes_man_cfg_err 5.000s 0.000us 50 50 100.00
aes_config_error 56.000s 0.000us 50 50 100.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
trigger_clear_test 50 50 100.00
aes_clear 18.000s 0.000us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 19.000s 0.000us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 11.000s 0.000us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
stress 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
sideload 100 100 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_sideload 21.000s 0.000us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 17.000s 0.000us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 68.000s 0.000us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 21.000s 0.000us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 0.000us 5 5 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 3.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 3.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 0.000us 5 5 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 3.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 3.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 18.000s 0.000us 50 50 100.00
fault_inject 678 700 96.86
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 27.000s 0.000us 5 5 100.00
aes_tl_intg_err 3.000s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_main_config_sparse 218 220 99.09
aes_smoke 9.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
aes_core_fi 41.000s 0.000us 69 70 98.57
sec_cm_gcm_config_sparse 269 270 99.63
aes_gcm_save_restore 21.000s 0.000us 100 100 100.00
aes_config_error 56.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_core_fi 41.000s 0.000us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 0.000us 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 66.000s 0.000us 50 50 100.00
aes_sideload 21.000s 0.000us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 66.000s 0.000us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 12.000s 0.000us 50 50 100.00
sec_cm_main_fsm_redun 728 750 97.07
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 12.000s 0.000us 50 50 100.00
sec_cm_cipher_fsm_redun 678 700 96.86
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
sec_cm_cipher_ctr_redun 340 350 97.14
aes_cipher_fi 37.000s 0.000us 340 350 97.14
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 12.000s 0.000us 50 50 100.00
sec_cm_ctr_fsm_redun 388 400 97.00
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 12.000s 0.000us 50 50 100.00
sec_cm_ctrl_sparse 728 750 97.07
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 18.000s 0.000us 49 50 98.00
sec_cm_main_fsm_local_esc 728 750 97.07
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_cipher_fsm_local_esc 728 750 97.07
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_ctr_fsm_local_esc 388 400 97.00
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_ctr_fi 9.000s 0.000us 50 50 100.00
sec_cm_ghash_fsm_local_esc 140 140 100.00
aes_fi 12.000s 0.000us 50 50 100.00
aes_ghash_fi 10.000s 0.000us 90 90 100.00
sec_cm_data_reg_local_esc 678 700 96.86
aes_fi 12.000s 0.000us 50 50 100.00
aes_control_fi 35.000s 0.000us 288 300 96.00
aes_cipher_fi 37.000s 0.000us 340 350 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 42.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 109604692663704315613248165123129583457840191473811266968737719052456268002412 672
UVM_FATAL @ 6984590167 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 6984590167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 46111729531609052529888925503037504877016364238561702496340495256637816902856 897
UVM_FATAL @ 2767699218 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 2767699218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 34919087155594326592801981446518873024548319558011796739358134208866100707694 158
UVM_FATAL @ 18638244 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 18638244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 44200939898840714804595133003451045428875890759799386979330214911568910461136 166
UVM_FATAL @ 120698169 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 120698169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 104655377174294095507876254971967716805315625701211542671342881150006875278649 213
UVM_FATAL @ 123189414 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 123189414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_control_fi 113960241962056927648245946371028266290487073182329046755444837954466983078411 None
Job timed out after 1 minutes
aes_control_fi 100714717305845384525832886875438347205237486281054589907904871871337889027 None
Job timed out after 1 minutes
aes_cipher_fi 30032215268514882999741137748184563362904684761592030257983989960599051239167 None
Job timed out after 1 minutes
aes_control_fi 5592493849353049763481551307981943983121889594488598608633372935842182148927 None
Job timed out after 1 minutes
aes_control_fi 32607306350450492591098000852604735558188334554330691429381935769401506064526 None
Job timed out after 1 minutes
aes_control_fi 79839247269517297350328140556906695887817682559337863725222584994200654272328 None
Job timed out after 1 minutes
aes_control_fi 62041187423840742436420127582736067563797312510699704228062915698500596289291 None
Job timed out after 1 minutes
aes_cipher_fi 81661679762360802709991313396909709257037013258179299893650472634636638799014 None
Job timed out after 1 minutes
aes_cipher_fi 33523051124082228545070245495732880265437234242853181383998712084130486304545 None
Job timed out after 1 minutes
aes_control_fi 4170823766349280342490632341547517689476317342818276563343728879665713232376 None
Job timed out after 1 minutes
aes_cipher_fi 22217859010900445630173414908782695355576466361386361948347026297393313170098 None
Job timed out after 1 minutes
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 105186248578880346621678116633951585718235266628345551018647906998505590369449 1259
UVM_ERROR @ 3065163570 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3065163570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 26750439622041191979800892203419769030469596165764949874560045540353871160695 201
UVM_ERROR @ 230316999 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 230316999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 3348710217315092693657311781067860902333202376039908131260888546531544339599 389
UVM_ERROR @ 1225563773 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1225563773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
aes_stress_all_with_rand_reset 22425170427380217713926908745412054680714827839689485771699188733585730736632 887
UVM_FATAL @ 770892439 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
UVM_INFO @ 770892439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 80760381449747816150021530465343958847610550583655653332955623488052010568925 207
UVM_ERROR @ 279926186 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 279926186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed
aes_alert_reset 35472094925411402814551942514394661581292599230928162256094018206752304684325 876
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1112): (time 11616687 PS) Assertion tb.dut.u_aes_core.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 11616687 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 11616687 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 11616687 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 11616687 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 55043083302769515594813634547910730897407934481989153600320554007012659040827 146
UVM_FATAL @ 10031004609 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10031004609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 35758249074803120351283633620186218133825246764299347377516700508676739672189 141
UVM_FATAL @ 10043979510 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10043979510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95174273490065988076984513564677590330013748289775790257032355474878032184065 151
UVM_FATAL @ 10018597915 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10018597915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 31623995354153649123266065720543399297265801797382564703793823356571746437379 154
UVM_FATAL @ 10008869043 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008869043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76369145812374249097981005868645240367991976629003861610696349246787994694174 143
UVM_FATAL @ 10063037160 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10063037160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 72014541808775383946357823289107521788668859011235802691014997236361156287496 146
UVM_FATAL @ 10010281119 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010281119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38010209495084084681831979362582738431782003841807576756885454098895531798764 152
UVM_FATAL @ 10009711108 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009711108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 32703202535617064057689822156340042380146394153479103488043178080669964015705 147
UVM_FATAL @ 10023200675 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023200675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 66430121477767101810333711451042837174497460957977209805718852215549537522984 149
UVM_FATAL @ 10005993780 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005993780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93691339138981259548802316507868922794497488479216304806315723257878512306862 151
UVM_FATAL @ 10025615008 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10025615008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 31411540688334832352896474289066727810858859693289243504785808797449426022860 141
UVM_FATAL @ 10026613949 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10026613949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69368833941761839249615004466897033243674801413333195205754211285738931233327 148
UVM_FATAL @ 10058642223 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10058642223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---