Simulation Results: dma

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.45 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 80.18 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 0.000us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 0.000us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 10.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 31.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 31.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 36.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 36.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 31.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 31.000s 0.000us 20 20 100.00
dma_csr_aliasing 36.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 134.000s 0.000us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 839.000s 0.000us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 690.000s 0.000us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 690.000s 0.000us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 839.000s 0.000us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1493.000s 0.000us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 690.000s 0.000us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 28.000s 0.000us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 415.000s 0.000us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 30.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 32.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 32.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 31.000s 0.000us 5 5 100.00
dma_csr_rw 31.000s 0.000us 20 20 100.00
dma_csr_aliasing 36.000s 0.000us 5 5 100.00
dma_same_csr_outstanding 31.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 31.000s 0.000us 5 5 100.00
dma_csr_rw 31.000s 0.000us 20 20 100.00
dma_csr_aliasing 36.000s 0.000us 5 5 100.00
dma_same_csr_outstanding 31.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 28.000s 0.000us 5 5 100.00
dma_generic_stress 1493.000s 0.000us 5 5 100.00
dma_handshake_stress 690.000s 0.000us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 13.000s 0.000us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 32.000s 0.000us 20 20 100.00
dma_sec_cm 2.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 190.000s 0.000us 25 25 100.00
dma_longer_transfer 9.000s 0.000us 5 5 100.00
dma_stress_all_with_rand_reset 4.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 2781694017324489629449593634524526068272950194957093843004306203837062780245 91
UVM_ERROR @ 123003839ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123003839ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---