Simulation Results: edn/edn0

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 95.72 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.08 %
  • toggle
  • 97.17 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.160s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.990s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.970s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.710s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.500s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.720s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.970s 0.000us 20 20 100.00
edn_csr_aliasing 1.500s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 129.990s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 129.990s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 129.990s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.300s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.430s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.400s 0.000us 100 100 100.00
disable 100 100 100.00
edn_disable 1.150s 0.000us 50 50 100.00
edn_disable_auto_req_mode 1.570s 0.000us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 6.210s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.950s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.180s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.360s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.360s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.990s 0.000us 5 5 100.00
edn_csr_rw 0.970s 0.000us 20 20 100.00
edn_csr_aliasing 1.500s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.330s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.990s 0.000us 5 5 100.00
edn_csr_rw 0.970s 0.000us 20 20 100.00
edn_csr_aliasing 1.500s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.330s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
edn_tl_intg_err 4.770s 0.000us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.060s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.430s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.430s 0.000us 200 200 100.00
edn_sec_cm 7.900s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.430s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.770s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 134.740s 0.000us 50 50 100.00