Simulation Results: gpio

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.48 %
  • code
  • 92.61 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 98.38 %
  • cond
  • 95.61 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
98.57%
V2
91.49%
V2S
91.11%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.150s 0.000us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.200s 0.000us 50 50 100.00
gpio_smoke_en_cdc_prim 1.140s 0.000us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.190s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 0.770s 0.000us 5 5 100.00
csr_rw 19 20 95.00
gpio_csr_rw 0.870s 0.000us 19 20 95.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 5.970s 0.000us 5 5 100.00
csr_aliasing 4 5 80.00
gpio_csr_aliasing 1.860s 0.000us 4 5 80.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.280s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 23 25 92.00
gpio_csr_rw 0.870s 0.000us 19 20 95.00
gpio_csr_aliasing 1.860s 0.000us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.170s 0.000us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.010s 0.000us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 0.890s 0.000us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.110s 0.000us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 2.440s 0.000us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 2.430s 0.000us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 16.200s 0.000us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 4.240s 0.000us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 0.990s 0.000us 50 50 100.00
stress_all 1 50 2.00
gpio_stress_all 40.530s 0.000us 1 50 2.00
alert_test 50 50 100.00
gpio_alert_test 0.670s 0.000us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.730s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 2.520s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 2.520s 0.000us 20 20 100.00
tl_d_outstanding_access 43 50 86.00
gpio_csr_rw 0.870s 0.000us 19 20 95.00
gpio_same_csr_outstanding 1.250s 0.000us 15 20 75.00
gpio_csr_aliasing 1.860s 0.000us 4 5 80.00
gpio_csr_hw_reset 0.770s 0.000us 5 5 100.00
tl_d_partial_access 43 50 86.00
gpio_csr_rw 0.870s 0.000us 19 20 95.00
gpio_same_csr_outstanding 1.250s 0.000us 15 20 75.00
gpio_csr_aliasing 1.860s 0.000us 4 5 80.00
gpio_csr_hw_reset 0.770s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
gpio_sec_cm 0.860s 0.000us 5 5 100.00
gpio_tl_intg_err 2.200s 0.000us 18 20 90.00
sec_cm_bus_integrity 18 20 90.00
gpio_tl_intg_err 2.200s 0.000us 18 20 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 40 50 80.00
gpio_rand_straps 0.700s 0.000us 40 50 80.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 13.220s 0.000us 0 50 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.680s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
gpio_stress_all 41020613954400225371759073583588524287627580335923204673702501408523399092098 76
UVM_ERROR @ 119731523 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (166474484 [0x9ec32f4] vs 438220448 [0x1a1eb6a0])
UVM_INFO @ 119731523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13731258792458660709694994618369973046229819031469258365337962599979092121298 76
UVM_ERROR @ 356240134 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2887067484 [0xac15275c] vs 1509155779 [0x59f3e3c3])
UVM_INFO @ 356240134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75870071556241948474532131037625997326227397972860671750884460972204599864701 1517
UVM_ERROR @ 18335668138 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 635759235 [0x25e4ea83])
UVM_INFO @ 18335668138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 33031310882971121980892849737178772922769463706374486850235781772033709636767 165
UVM_ERROR @ 463459750 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2491303673 [0x947e46f9])
UVM_INFO @ 463459750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 42991177368169205092053344684644677959793921495048300976978841573593569080953 1396
UVM_ERROR @ 6388594125 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2877480209 [0xab82dd11])
UVM_INFO @ 6388594125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 60208638349020378906709916385835984713880784382455437239820803342183557565165 75
UVM_ERROR @ 204528394 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (602869589 [0x23ef0f55] vs 2424511504 [0x90831c10])
UVM_INFO @ 204528394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 13763233062113094463299682088999777739739218912788656350680830296100149156747 75
UVM_ERROR @ 16203431 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2575096254 [0x997cd9be])
UVM_INFO @ 16203431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 50085347546727299304895865504912903153258677085410594727194080245982974457891 77
UVM_ERROR @ 202901158 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4146769530 [0xf72aae7a])
UVM_INFO @ 202901158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100285028363562249170247312245614382868804119772958086439894539735580969482775 1096
UVM_ERROR @ 17048246614 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3166973757 [0xbcc42f3d] vs 2710561325 [0xa18fe22d])
UVM_INFO @ 17048246614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 4427391434391902708661774397291119402357219357012676846932053522559587215741 118
UVM_ERROR @ 1171760386 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2152794521 [0x80510999])
UVM_INFO @ 1171760386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 98505280985458265723004366074931017412331206607191983516312279596383124362576 668
UVM_ERROR @ 1449461946 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3430680070 [0xcc7c0606])
UVM_INFO @ 1449461946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26029712012011293234313987230670059534591393070858820760618135603143937623792 574
UVM_ERROR @ 2456005581 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (566944312 [0x21cae238] vs 1527525736 [0x5b0c3168])
UVM_INFO @ 2456005581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 48382562602605070152261696300035198265235147967209676366482807042721356209745 1756
UVM_ERROR @ 4702544881 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2792571314 [0xa67341b2] vs 896068221 [0x3568ea7d])
UVM_INFO @ 4702544881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 51709613393923132147630332766304203928291768443075469559436947006321110820216 244
UVM_ERROR @ 1710677276 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3688297771 [0xdbd6f52b])
UVM_INFO @ 1710677276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58083489244437614160649362406698226661297321964345725248787416819785697874480 804
UVM_ERROR @ 8215626142 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (340671070 [0x144e3a5e] vs 2379906680 [0x8dda7e78])
UVM_INFO @ 8215626142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46324079417491186863692688710048064100188972682766366857956226630123231969117 1303
UVM_ERROR @ 20538735652 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1535136400 [0x5b805290] vs 19876073 [0x12f48e9])
UVM_INFO @ 20538735652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32076136567219882608317280011953557242867713276337690138146604604593898676422 1092
UVM_ERROR @ 9327652142 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3520395520 [0xd1d4f900])
UVM_INFO @ 9327652142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 20979646928085395407629240213525199850241225953222661791906728389815029155490 78
UVM_ERROR @ 183744188 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 4073277799 [0xf2c94967])
UVM_INFO @ 183744188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 39823368248916907972081874420087882064100369830708181269035074485916615233386 75
UVM_ERROR @ 896880 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 1424929952 [0x54eeb4a0])
UVM_INFO @ 896880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 33142041968476436359644061888916494944507099508402402461105050689980058893281 156
UVM_ERROR @ 977595728 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3348127929 [0xc79060b9] vs 3794417739 [0xe22a384b])
UVM_INFO @ 977595728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 6652902518674643361039028043349699829883012090078377662292134285543409613988 1618
UVM_ERROR @ 4291955366 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 1093238520 [0x41297ef8])
UVM_INFO @ 4291955366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 88946752080841626374460698790809803795719331216114043852014530103594396110635 712
UVM_ERROR @ 1235010676 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2714389802 [0xa1ca4d2a])
UVM_INFO @ 1235010676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 69471438805600792250215051490044106622277016614672013945316748280195222287534 78
UVM_ERROR @ 301966888 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (455645127 [0x1b2897c7] vs 19335311 [0x127088f])
UVM_INFO @ 301966888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 79086052106546403097720188870419906418996819647653346930991381566860107029971 75
UVM_ERROR @ 9124482 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1556992105 [0x5ccdd069])
UVM_INFO @ 9124482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1075378648871274762193640663578279047970344655933747165834720285108831650740 330
UVM_ERROR @ 3175508047 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (293411584 [0x117d1b00] vs 1286356433 [0x4cac3dd1])
UVM_INFO @ 3175508047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 76270940084461040846116220323321858392471812401822902415800180931797293833849 649
UVM_ERROR @ 2990382707 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 628927247 [0x257cab0f])
UVM_INFO @ 2990382707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 105605111182604740460368725223042770472206818326643787815128367503799722011428 543
UVM_ERROR @ 4676002742 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3719733380 [0xddb6a084] vs 734077353 [0x2bc121a9])
UVM_INFO @ 4676002742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75644075086329887139046837688762564149369648542311926283548062833415461864490 228
UVM_ERROR @ 729555136 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2033497695 [0x7934b65f] vs 2563408337 [0x98ca81d1])
UVM_INFO @ 729555136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1167768020383081536453305849506662520349469296188787014226243653860261621841 79
UVM_ERROR @ 515558161 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3588895123 [0xd5ea3193])
UVM_INFO @ 515558161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 10560928161210423045339675573070732507793131693192654232788717591302880018192 75
UVM_ERROR @ 941156 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 1302931111 [0x4da926a7])
UVM_INFO @ 941156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79073792015927279297733513174828849893253335448975458838166690659000520667072 200
UVM_ERROR @ 2129244161 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3397967184 [0xca88dd50])
UVM_INFO @ 2129244161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 86050525312937784169577137801287648747970294432776835817859210007783705028756 75
UVM_ERROR @ 4940459 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 4188804310 [0xf9ac14d6])
UVM_INFO @ 4940459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 87991550791747974150769522749029717789914888979652272357172245578187735331747 334
UVM_ERROR @ 358373019 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 860428961 [0x33491aa1])
UVM_INFO @ 358373019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11488559405430740295887878387922498661709421168172082428808879448614760986263 314
UVM_ERROR @ 1710164260 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 6498640 [0x632950])
UVM_INFO @ 1710164260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11398652263541896918152294869837490454995150145399962345361907545488948283941 371
UVM_ERROR @ 884552734 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3816264658 [0xe37793d2])
UVM_INFO @ 884552734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10036433578031413405497046197650843171683480658687389761036783635822570428933 79
UVM_ERROR @ 1703783018 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3581974316 [0xd580972c] vs 1043030212 [0x3e2b60c4])
UVM_INFO @ 1703783018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97634549590987778432792968984360036268031887602165400095167701944031987809553 76
UVM_ERROR @ 4190340 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2366590971 [0x8d0f4ffb])
UVM_INFO @ 4190340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 73253853502140031220204573576150456561471880113548500063865476251023339040056 75
UVM_ERROR @ 1245290 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 836697287 [0x31defcc7])
UVM_INFO @ 1245290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58480118624274738338234943013304113532803773259408091176770859052109881941182 556
UVM_ERROR @ 1500400102 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2751260647 [0xa3fce7e7] vs 3689576182 [0xdbea76f6])
UVM_INFO @ 1500400102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 59414810984802506674583269330871765231225313265624374000771024973028798842990 76
UVM_ERROR @ 11175399 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4025641561 [0xeff26a59])
UVM_INFO @ 11175399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 48770500662630159096484216147290080705812794894424493581326521316160707370488 75
UVM_ERROR @ 11358263 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3530972610 [0xd2765dc2])
UVM_INFO @ 11358263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 52106794913608106162313709667326603309823781855578996633402700078154999399799 533
UVM_ERROR @ 1002665557 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 502904384 [0x1df9b640])
UVM_INFO @ 1002665557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 3695809802955019935909440843707338340884084453636192307969364765087804839155 75
UVM_ERROR @ 31207942 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 453979681 [0x1b0f2e21])
UVM_INFO @ 31207942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 82808092347464226844303285617921351925550284946352037540977072083257502554382 75
UVM_ERROR @ 28054233 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1807160691 [0x6bb71573] vs 3310199201 [0xc54da1a1])
UVM_INFO @ 28054233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 36136089180166160728650903663520523897423142709268772885359248740699423017904 931
UVM_ERROR @ 2052968985 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1101894918 [0x41ad9506])
UVM_INFO @ 2052968985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83844619166718413513221937277893752894589056800456955759183698881176645005507 356
UVM_ERROR @ 1253177242 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 4242293242 [0xfcdc41fa])
UVM_INFO @ 1253177242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 18000746153256913949691485035750244405044057580916585403004306506640907226342 611
UVM_ERROR @ 2929407218 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2627145161 [0x9c970dc9])
UVM_INFO @ 2929407218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10249415564023187174561987534154506628102609089757927081555302965456706915020 1375
UVM_ERROR @ 12916210364 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2452531861 [0x922eaa95])
UVM_INFO @ 12916210364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46623925339058901894451553789348276180646545431749077994942046723582371655122 240
UVM_ERROR @ 277419589 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1971416366 [0x75816d2e] vs 627136515 [0x25615803])
UVM_INFO @ 277419589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97722336301981712445874305114224601493274809365833340693083274000360127262965 661
UVM_ERROR @ 6639836881 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 2818602132 [0xa8007494])
UVM_INFO @ 6639836881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71020979886052518683866574677612222038413550512838034267701067862415456402058 264
UVM_ERROR @ 226613994 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4294967295 [0xffffffff] vs 3658146886 [0xda0ae446])
UVM_INFO @ 226613994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 62273483268806571918824977141915518569960832268586963215930665410763240472608 1633
UVM_ERROR @ 2229109144 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (699256425 [0x29adce69] vs 1851347759 [0x6e59532f])
UVM_INFO @ 2229109144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 76681900995028717741659061974734791334461238684569935829126454856196491171735 433
UVM_ERROR @ 463340262 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1130033557 [0x435af195] vs 97291053 [0x5cc8b2d])
UVM_INFO @ 463340262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 69695138614701513637419617372571588977573571486087964494767506190627686975546 75
UVM_ERROR @ 1303749 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4062528410 [0xf225439a])
UVM_INFO @ 1303749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53145573486941313634335600726139467609276609008151172257723816912999163116076 77
UVM_ERROR @ 686415515 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4060814672 [0xf20b1d50])
UVM_INFO @ 686415515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 31511827656679562350174510922724198243611967291214351777550730745354590410845 937
UVM_ERROR @ 2687526180 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 730759345 [0x2b8e80b1])
UVM_INFO @ 2687526180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 5313312264037576690988055096325931729466668007400313388313651202529090697565 75
UVM_ERROR @ 2616847 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 961462029 [0x394ebf0d])
UVM_INFO @ 2616847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 91903377577434038302673687737976589351020114327226173653007456177164339563919 1133
UVM_ERROR @ 2056762748 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 419632978 [0x19031752])
UVM_INFO @ 2056762748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84416485949281099889846412499073963259109856455761059703761279638377892010377 88
UVM_ERROR @ 3675761140 ps: (gpio_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3344296323 [0xc755e983])
UVM_INFO @ 3675761140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -*
gpio_stress_all_with_rand_reset 46265829472258756238048659334599259282766819694733391238163916213549337155936 80
UVM_FATAL @ 9217554 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 9217554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 96367918669904060870972933906295679190510501008308355073666672769416620386957 78
UVM_FATAL @ 7836799 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 7836799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 104406732040845748491224834496393337622227665699239725195245933034971111946982 82
UVM_FATAL @ 347991745 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 347991745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 4887701242947626814287709498759696934914458083944357393547508082011763201578 78
UVM_FATAL @ 72049167 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 72049167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30045514191811381694092537891598577282305115960554727430821812358366514983751 78
UVM_FATAL @ 5747534 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 5747534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 48241529515160355768572895420145518380455452533600451783598977387976178786576 79
UVM_FATAL @ 565668354 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 565668354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100042709971361026145178240230567004977255524955990404664463389829904815649593 389
UVM_FATAL @ 1531213209 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1531213209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 36969726211604943709061946606277754538269512446556240678295755082778626083928 82
UVM_FATAL @ 263967166 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 263967166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54659757889150441815271370357047260829576650299736957514851259704649125222948 78
UVM_FATAL @ 2732081 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 2732081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 69026894502361503677649399730425772643568663572469381270725644192597072256007 78
UVM_FATAL @ 9695109 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 9695109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 99351289802312224719511801978568117143371477001924194060987081681391084979036 356
UVM_FATAL @ 1111404448 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1111404448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 21552912622582426141383394175365462683137763210758035763106287155323762081681 78
UVM_FATAL @ 101171843 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 101171843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 4060954721293144709710441381877753524281000137665269779753802296278915076339 81
UVM_FATAL @ 347713839 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 347713839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 18825403809544297252214734800018723404825333089772088825746133409483034390333 154
UVM_FATAL @ 66642250 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 66642250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 94632039489589423417885086741574152763530260119473234638097241415034560440607 82
UVM_FATAL @ 2330547576 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 2330547576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 36623639947619136391698093649448285387695322569983004401674454984097931961195 78
UVM_FATAL @ 10239703 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 10239703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 49409568367405389358318263046533211784355442590663145199832559148679383407849 78
UVM_FATAL @ 350281861 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 350281861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 26792334295437344719516159972724407318491896081811277859230401079112455928448 80
UVM_FATAL @ 2885264 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 2885264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24921911232287630798019239793992596788589685048707195221215122187097752783054 78
UVM_FATAL @ 179901716 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 179901716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 83519305992410500951816717477799516468396957414344815060956471964365747255953 78
UVM_FATAL @ 1461839 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1461839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 45019329152156910491667751253728605860692428868001130298486174813994853107798 81
UVM_FATAL @ 1660722150 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1660722150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 94637130130051283056671441258232136514317599977273203427190045150900818019444 78
UVM_FATAL @ 2033787 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 2033787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39334329144763288261782981049338559750699155393646343937582805429474444676599 105
UVM_FATAL @ 223814544 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 223814544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 7573035885448335951476122574772031537812605373197684544848048143650815770552 78
UVM_FATAL @ 569548054 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 569548054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 86032025955855764118335702311376224598641220815464465727849060478208557787820 78
UVM_FATAL @ 196661928 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 196661928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 112453890136834122798577347862666320367531604196314078268026681574646246566099 411
UVM_FATAL @ 349290192 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 349290192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done)
gpio_stress_all_with_rand_reset 62463006699084001681165840185952816476904403872347939007811689119526377781966 226
UVM_FATAL @ 563934731 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 563934731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 9444793079623149989567527275365130969583681158947626582056775624107572165834 616
UVM_FATAL @ 1958380480 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1958380480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 32467716323390178470353817349558633863363014401673335571396204544093154609964 245
UVM_FATAL @ 2748431378 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2748431378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 63699775572812985608419777833136276746977177872493361144581603575116314666994 383
UVM_FATAL @ 916845765 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 916845765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 105025062191039805706358526346227448812794725632847474588170556697274842038631 80
UVM_FATAL @ 7629142 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 7629142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101239681872326528664989430379634526514566853960020070875676434409514916440514 84
UVM_FATAL @ 337773983 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 337773983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66695727485767741691967155443101164383674464928231094478336111645767423700994 80
UVM_FATAL @ 51994850 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 51994850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 13336252998176574611418338925763994577911081908596358141130256617653439474784 82
UVM_FATAL @ 213228302 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 213228302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 81416760930067097940874727650093392908218347406004263689280509903049745621768 80
UVM_FATAL @ 5813898 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5813898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 102621318932257804865419944685585605666706613342711725812125850520998951475509 80
UVM_FATAL @ 1733053 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1733053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 97450248035776768556512777455236802363615280109027867939537292435124498283040 205
UVM_FATAL @ 673761668 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 673761668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 37171478757148082983357962398415859628581660629521231560599914007901110308779 82
UVM_FATAL @ 17130155 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 17130155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111621690079502212146255557460867781041995162611603344525361734469128641006337 80
UVM_FATAL @ 6016582 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 6016582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 94051335514479620482930455527360612241315367886333907094151096861310352950351 82
UVM_FATAL @ 13838688 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 13838688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115335376963741281155699591605450157207026225431305915512025936919324410720457 80
UVM_FATAL @ 51559324 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 51559324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31994733096836934132772532221058334316980617326049726859545130137643621842101 84
UVM_FATAL @ 21507941 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 21507941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51329121776040459695739127657333751267294208673696627614239477300425820936963 300
UVM_FATAL @ 1967578275 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1967578275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 20778661371851024437918687606097118939014925199335529445436734653403283669754 80
UVM_FATAL @ 3248072 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3248072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100517736948432626010578676084730009393509831341915445042708608209964530051182 83
UVM_FATAL @ 317159735 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 317159735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66572443027341215091635438450641821317443235749274896553243861672200717669622 80
UVM_FATAL @ 23073536 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 23073536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30442591243602916794463607782460022317747957133454020638378386701572211791087 123
UVM_FATAL @ 783952500 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 783952500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 40338354856174954933581347842383568216592223249354669134883074050351638597189 80
UVM_FATAL @ 37115891 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 37115891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 70359920035000272545438819645604279182243157890534834441409734686364559482086 82
UVM_FATAL @ 96885267 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 96885267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66115619107781769988949888721159800050656616741381363537096391576615857880191 82
UVM_FATAL @ 904701075 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 904701075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: *
gpio_csr_aliasing 105943144269463295258797988830039571468101399319291425748618336034079182647650 77
UVM_ERROR @ 43308519 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 0 [0x0]) Regname: gpio_reg_block.inp_prd_cnt_val_4 reset value: 0x0
UVM_INFO @ 43308519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
gpio_same_csr_outstanding 59073772210309909387980499547624580894028515028072969071466365456191820379292 79
UVM_ERROR @ 92468131 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (11061248 [0xa8c800] vs 11061249 [0xa8c801]) addr 0xf5cb1760 read out mismatch
UVM_INFO @ 92468131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 82663798107235150389864409260152242831249279556997334970208805975395649912116 77
UVM_ERROR @ 31110771 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x20860280 read out mismatch
UVM_INFO @ 31110771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 115344972755733518527443332575209958973718303077612801261342924652679622497661 77
UVM_ERROR @ 180650816 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (15453952 [0xebcf00] vs 15453953 [0xebcf01]) addr 0xfb1ffd4c read out mismatch
UVM_INFO @ 180650816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 66002901496287679173890487421977944008245382199456504070803930530742382875339 77
UVM_ERROR @ 179443057 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (10230272 [0x9c1a00] vs 10230273 [0x9c1a01]) addr 0x7bfdc164 read out mismatch
UVM_INFO @ 179443057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 12997024645640144230299573728830430575974999430928098012827122206822042103947 76
UVM_ERROR @ 90928560 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (2 [0x2] vs 0 [0x0]) addr 0xd7a72e68 read out mismatch
UVM_INFO @ 90928560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_*.value_* reset value: *
gpio_csr_rw 21268396255712449567447029268502376903123074848249571024521060799393233049348 78
UVM_ERROR @ 103540451 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 0 [0x0]) Regname: gpio_reg_block.inp_prd_cnt_val_6.value_0 reset value: 0x0
UVM_INFO @ 103540451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: *
gpio_tl_intg_err 83364566281529492779248617061827697668887770816529930775979562798854491559420 110
UVM_ERROR @ 59038780 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_4.enable reset value: 0x0
UVM_INFO @ 59038780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_tl_intg_err 12555051576625795474920665761188976795731169710114136359449373526661206067093 130
UVM_ERROR @ 630640461 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_7.enable reset value: 0x0
UVM_INFO @ 630640461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---