Simulation Results: hmac

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.45 %
  • code
  • 98.64 %
  • assert
  • 96.70 %
  • func
  • 100.00 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.810s 0.000us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.150s 0.000us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.280s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.380s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 9.330s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 793.930s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.280s 0.000us 20 20 100.00
hmac_csr_aliasing 9.330s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 85.290s 0.000us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 88.330s 0.000us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 252.150s 0.000us 30 30 100.00
hmac_test_sha384_vectors 546.640s 0.000us 75 75 100.00
hmac_test_sha512_vectors 565.730s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 16.520s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.370s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 0.000us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.630s 0.000us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 713.180s 0.000us 10 10 100.00
error 10 10 100.00
hmac_error 108.020s 0.000us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 142.380s 0.000us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.810s 0.000us 10 10 100.00
hmac_long_msg 85.290s 0.000us 10 10 100.00
hmac_back_pressure 88.330s 0.000us 25 25 100.00
hmac_datapath_stress 713.180s 0.000us 10 10 100.00
hmac_burst_wr 47.630s 0.000us 50 50 100.00
hmac_stress_all 1806.840s 0.000us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.810s 0.000us 10 10 100.00
hmac_long_msg 85.290s 0.000us 10 10 100.00
hmac_back_pressure 88.330s 0.000us 25 25 100.00
hmac_datapath_stress 713.180s 0.000us 10 10 100.00
hmac_wipe_secret 142.380s 0.000us 10 10 100.00
hmac_test_sha256_vectors 252.150s 0.000us 30 30 100.00
hmac_test_sha384_vectors 546.640s 0.000us 75 75 100.00
hmac_test_sha512_vectors 565.730s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 16.520s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.370s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 0.000us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.810s 0.000us 10 10 100.00
hmac_long_msg 85.290s 0.000us 10 10 100.00
hmac_back_pressure 88.330s 0.000us 25 25 100.00
hmac_datapath_stress 713.180s 0.000us 10 10 100.00
hmac_burst_wr 47.630s 0.000us 50 50 100.00
hmac_error 108.020s 0.000us 10 10 100.00
hmac_wipe_secret 142.380s 0.000us 10 10 100.00
hmac_test_sha256_vectors 252.150s 0.000us 30 30 100.00
hmac_test_sha384_vectors 546.640s 0.000us 75 75 100.00
hmac_test_sha512_vectors 565.730s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 16.520s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.370s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 0.000us 75 75 100.00
hmac_stress_all 1806.840s 0.000us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1806.840s 0.000us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 0.000us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.940s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.590s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.590s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.150s 0.000us 5 5 100.00
hmac_csr_rw 1.280s 0.000us 20 20 100.00
hmac_csr_aliasing 9.330s 0.000us 5 5 100.00
hmac_same_csr_outstanding 2.760s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.150s 0.000us 5 5 100.00
hmac_csr_rw 1.280s 0.000us 20 20 100.00
hmac_csr_aliasing 9.330s 0.000us 5 5 100.00
hmac_same_csr_outstanding 2.760s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.280s 0.000us 5 5 100.00
hmac_tl_intg_err 5.270s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.270s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.810s 0.000us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 5.740s 0.000us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 431.930s 0.000us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.950s 0.000us 1 1 100.00