Simulation Results: keymgr_dpe

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.41 %
  • code
  • 84.22 %
  • assert
  • 97.64 %
  • func
  • 17.36 %
  • line
  • 97.67 %
  • branch
  • 94.50 %
  • cond
  • 90.12 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
99.17%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_dpe_smoke 216.100s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.260s 0.000us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.440s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 12.380s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 6.180s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.930s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.440s 0.000us 20 20 100.00
keymgr_dpe_csr_aliasing 6.180s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.090s 0.000us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.810s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 3.730s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 3.730s 0.000us 20 20 100.00
tl_d_outstanding_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.260s 0.000us 5 5 100.00
keymgr_dpe_csr_rw 1.440s 0.000us 20 20 100.00
keymgr_dpe_csr_aliasing 6.180s 0.000us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.490s 0.000us 19 20 95.00
tl_d_partial_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.260s 0.000us 5 5 100.00
keymgr_dpe_csr_rw 1.440s 0.000us 20 20 100.00
keymgr_dpe_csr_aliasing 6.180s 0.000us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.490s 0.000us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 6.500s 0.000us 20 20 100.00
keymgr_dpe_sec_cm 25.680s 0.000us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.300s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.300s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.300s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.300s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 6.720s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 25.680s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 25.680s 0.000us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:649) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
keymgr_dpe_same_csr_outstanding 19719878980507712891599881655461355364439540027876012325388225539180040705606 88
UVM_ERROR @ 38625919 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xe56a78d0 read out mismatch
UVM_INFO @ 38625919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---