Simulation Results: kmac/masked

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 94.26 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.79 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.88%
V2S
99.60%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 69.400s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.020s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.050s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 10.740s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.660s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.410s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.050s 0.000us 20 20 100.00
kmac_csr_aliasing 6.660s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.750s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.240s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3132.740s 0.000us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1212.020s 0.000us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 36.240s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 1838.640s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 1362.960s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 1041.520s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 1933.910s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 1330.950s 0.000us 5 5 100.00
kmac_test_vectors_kmac 2.980s 0.000us 5 5 100.00
kmac_test_vectors_kmac_xof 3.380s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 409.370s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 346.750s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 211.240s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 378.370s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 418.780s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.230s 0.000us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.600s 0.000us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 25.590s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 33.270s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 52.890s 0.000us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 45.860s 0.000us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 2625.290s 0.000us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 0.930s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.510s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.950s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.950s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.020s 0.000us 5 5 100.00
kmac_csr_rw 1.050s 0.000us 20 20 100.00
kmac_csr_aliasing 6.660s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.090s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.020s 0.000us 5 5 100.00
kmac_csr_rw 1.050s 0.000us 20 20 100.00
kmac_csr_aliasing 6.660s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.090s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.720s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.720s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.720s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.720s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
kmac_shadow_reg_errors_with_csr_rw 3.870s 0.000us 18 20 90.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.870s 0.000us 20 20 100.00
kmac_sec_cm 97.810s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.870s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 45.860s 0.000us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 69.400s 0.000us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 409.370s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.720s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 97.810s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 97.810s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 97.810s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 69.400s 0.000us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 45.860s 0.000us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 97.810s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 266.930s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 69.400s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 131.500s 0.000us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 43675504139840804693132333323309995195961321863132650813036659959555724239389 294
UVM_ERROR @ 98835476 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3301119308 [0xc4c3154c] vs 105369055 [0x647cddf]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
UVM_INFO @ 98835476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_shadow_reg_errors_with_csr_rw 39008208202467977975217826524468771461467942914565507621530644122550359346211 98
UVM_ERROR @ 2692107 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (967403689 [0x39a968a9] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
UVM_INFO @ 2692107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 97216514648958220136438787328316832442453869851352935240857699742192366778840 145
UVM_ERROR @ 4781285294 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4781285294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 96755939051834973512297442153347544714886621470806717967112459580462097402725 164
UVM_ERROR @ 44751592619 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 44751592619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---