Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.71 %
  • code
  • 88.95 %
  • assert
  • 96.13 %
  • func
  • 96.04 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.13 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
99.80%
V2S
100.00%
V3
38.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 4.860s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.390s 0.000us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.310s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.630s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.750s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.910s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.310s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.750s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 10.870s 0.000us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 24.200s 0.000us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.350s 0.000us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.430s 0.000us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 18.850s 0.000us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_prog_failure 5.430s 0.000us 50 50 100.00
lc_ctrl_errors 18.850s 0.000us 50 50 100.00
lc_ctrl_security_escalation 12.580s 0.000us 50 50 100.00
lc_ctrl_jtag_state_failure 55.890s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.230s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 94.250s 0.000us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 5.240s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.690s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 31.680s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.540s 0.000us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.820s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.820s 0.000us 10 10 100.00
lc_ctrl_jtag_alert_test 2.160s 0.000us 10 10 100.00
lc_ctrl_jtag_smoke 13.570s 0.000us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.680s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.230s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 94.250s 0.000us 20 20 100.00
lc_ctrl_jtag_access 15.780s 0.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.830s 0.000us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 26.260s 0.000us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.450s 0.000us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 403.480s 0.000us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.710s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.700s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.700s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.390s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.310s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.750s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.600s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.390s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.310s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.750s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.600s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.100s 0.000us 20 20 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.100s 0.000us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 24.200s 0.000us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 17.530s 0.000us 50 50 100.00
lc_ctrl_sec_cm 8.600s 0.000us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.580s 0.000us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 10.870s 0.000us 50 50 100.00
lc_ctrl_jtag_state_post_trans 23.680s 0.000us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.760s 0.000us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.760s 0.000us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 19.800s 0.000us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.290s 0.000us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.290s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 50 38.00
lc_ctrl_stress_all_with_rand_reset 104.730s 0.000us 19 50 38.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 108645732796565883570715724300488066813618785133736601374486438235927336807104 7185
UVM_ERROR @ 2195318582 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2195318582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55021959308862633984203845556174830503390250599870207311104512460407280087142 4541
UVM_ERROR @ 11189535116 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11189535116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45081153962939599309913365886772466981234456081618539824801085564136128515669 2335
UVM_ERROR @ 7626137462 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7626137462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33435599496112906164600141303277957745063461870798096882834597653306670561398 158
UVM_ERROR @ 993862465 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 993862465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 111784819658242158146184872691468444866204587532983658149267119964398475282045 742
UVM_ERROR @ 1534094371 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1534094371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24852299091263512139711722097757965225956547556671340254640908103946975364421 156
UVM_ERROR @ 567229533 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 567229533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14688129336020259046427005377054861714463195242077426266553774273837677701741 1265
UVM_ERROR @ 1767432070 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1767432070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64801571394752455257002349791079250434155278816305725150233601793284760690200 4009
UVM_ERROR @ 4455663024 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4455663024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34813569424407894467648134878906663266201660846527632174228858996175800033304 576
UVM_ERROR @ 2971889648 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2971889648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85235378730546771430757784837904267218684599123475782083578213879913455710796 1250
UVM_ERROR @ 5438557582 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5438557582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28153774893139115878592881055958894817910505495374235916432617254615712055859 16677
UVM_ERROR @ 4126495770 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4126495770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31055968631761373701281793669617274903269061208454217795187887175231692807787 5417
UVM_ERROR @ 1332784649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1332784649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53612460534360839223488174979370243148571638037060754896680907923843700204457 2017
UVM_ERROR @ 4564415492 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4564415492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70655070777134152409860414697684803932726472991283228577333339451799042851661 5990
UVM_ERROR @ 3051483890 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3051483890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27404603379631982129326456989333013840095840857924148959875253388886185259522 754
UVM_ERROR @ 1433440064 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1433440064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37697938155129591246630132836592294422040674916050937741943574253815498414094 4162
UVM_ERROR @ 1551387847 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1551387847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 977116851779975589884043366016946647587924049528687043980194492933264774844 5906
UVM_ERROR @ 9840421998 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9840421998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73846510034818805173679322428368372945267634472309149460194471476957540853083 179
UVM_ERROR @ 2440634574 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2440634574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22166008592601564546531506326529935861052262052543664422237878743967860890429 2088
UVM_ERROR @ 2619405495 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2619405495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45953590008729332562075480215734059101527885436816263236746514115737463897737 4537
UVM_ERROR @ 9957706760 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9957706760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35826608901118679249457084278345566162019967556105113473252287168793677377936 1171
UVM_ERROR @ 31122364727 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 31122364727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99013638696745994497058541867788851935774748305596571101085988495634324629606 1210
UVM_ERROR @ 967819719 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 967819719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48534051149445986627695440723582725421642445943300251725340118499150609680199 169
UVM_ERROR @ 4452671552 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4452671552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27415594298485390876552169303227741368503992204903314033800492729482474581216 2787
UVM_ERROR @ 1538663115 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1538663115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75335490027345845957178305079767309847946508391068679279642459358638197983307 165
UVM_ERROR @ 1297474802 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1297474802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15220497881828418512752009486574275921137651283674740034605272668736438338747 4204
UVM_ERROR @ 3904952923 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3904952923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45035563559255034391598318234261754151820213451480744376064901834053469611370 167
UVM_ERROR @ 4750105445 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4750105445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3658866055820790451544201631681579392644934682268022153976865617359015784324 11507
UVM_ERROR @ 13039128273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13039128273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20101158836739688102615656021851935334182719600753677753621228521581688455326 14536
UVM_ERROR @ 56009528553 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 56009528553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 74229067224444436043814077535314229023806322398782392652594068787042099366324 6246
UVM_ERROR @ 6294647580 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 6294647580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93671749378905195914833856612999796810297750486049647947207816913587263629774 4713
UVM_ERROR @ 7519236509 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 7519236509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 112193675472204776958791863024010827293593610431127573332250406832129510026158 9646
UVM_ERROR @ 6657888077 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6657888077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 47360225508072949584410492255880445301550699624607971024502864660242874596072 11293
UVM_ERROR @ 9552817782 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 9552817782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---