Simulation Results: rom_ctrl/32kb

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.55 %
  • code
  • 99.58 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.020s 0.000us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.140s 0.000us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.530s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.360s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.640s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.450s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.530s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 5.640s 0.000us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.590s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.130s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.990s 0.000us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 21.290s 0.000us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.260s 0.000us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.660s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 12.320s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 12.320s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.140s 0.000us 5 5 100.00
rom_ctrl_csr_rw 7.530s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 5.640s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.990s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.140s 0.000us 5 5 100.00
rom_ctrl_csr_rw 7.530s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 5.640s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.990s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.150s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_tl_intg_err 65.220s 0.000us 20 20 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.020s 0.000us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.020s 0.000us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.020s 0.000us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 65.220s 0.000us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
rom_ctrl_kmac_err_chk 7.260s 0.000us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 125.680s 0.000us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.150s 0.000us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 212.290s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 340.750s 0.000us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 40846222629987828875530991252325033874138751558345630304203379687397196343724 83
UVM_ERROR @ 376469703 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 376469703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 114515332204376816290785859480456655162343042445449551146825138713508267190625 87
UVM_ERROR @ 228307731 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 228307731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---