Simulation Results: rv_dm/use_dmi_interface

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.00 %
  • code
  • 75.38 %
  • assert
  • 96.24 %
  • func
  • 89.38 %
  • line
  • 91.22 %
  • branch
  • 77.35 %
  • cond
  • 78.27 %
  • toggle
  • 73.81 %
  • FSM
  • 56.25 %
Validation stages
V1
99.04%
V2
62.32%
V2S
97.59%
V3
20.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rv_dm_smoke 8.590s 0.000us 2 2 100.00
jtag_dtm_csr_hw_reset 5 5 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.860s 0.000us 5 5 100.00
jtag_dtm_csr_rw 20 20 100.00
rv_dm_jtag_dtm_csr_rw 2.640s 0.000us 20 20 100.00
jtag_dtm_csr_bit_bash 5 5 100.00
rv_dm_jtag_dtm_csr_bit_bash 19.690s 0.000us 5 5 100.00
jtag_dtm_csr_aliasing 5 5 100.00
rv_dm_jtag_dtm_csr_aliasing 3.290s 0.000us 5 5 100.00
jtag_dmi_csr_hw_reset 5 5 100.00
rv_dm_jtag_dmi_csr_hw_reset 11.570s 0.000us 5 5 100.00
jtag_dmi_csr_rw 20 20 100.00
rv_dm_jtag_dmi_csr_rw 42.820s 0.000us 20 20 100.00
jtag_dmi_csr_bit_bash 20 20 100.00
rv_dm_jtag_dmi_csr_bit_bash 106.570s 0.000us 20 20 100.00
jtag_dmi_csr_aliasing 5 5 100.00
rv_dm_jtag_dmi_csr_aliasing 158.640s 0.000us 5 5 100.00
jtag_dmi_cmderr_busy 2 2 100.00
rv_dm_cmderr_busy 3.170s 0.000us 2 2 100.00
jtag_dmi_cmderr_not_supported 2 2 100.00
rv_dm_cmderr_not_supported 1.590s 0.000us 2 2 100.00
cmderr_exception 2 2 100.00
rv_dm_cmderr_exception 1.520s 0.000us 2 2 100.00
mem_tl_access_resuming 0 2 0.00
rv_dm_mem_tl_access_resuming 2.280s 0.000us 0 2 0.00
mem_tl_access_halted 2 2 100.00
rv_dm_mem_tl_access_halted 2.590s 0.000us 2 2 100.00
cmderr_halt_resume 2 2 100.00
rv_dm_cmderr_halt_resume 1.880s 0.000us 2 2 100.00
dataaddr_rw_access 2 2 100.00
rv_dm_dataaddr_rw_access 1.130s 0.000us 2 2 100.00
halt_resume 8 8 100.00
rv_dm_halt_resume_whereto 2.430s 0.000us 8 8 100.00
progbuf_busy 2 2 100.00
rv_dm_cmderr_busy 3.170s 0.000us 2 2 100.00
abstractcmd_status 2 2 100.00
rv_dm_abstractcmd_status 1.620s 0.000us 2 2 100.00
progbuf_read_write_execute 2 2 100.00
rv_dm_progbuf_read_write_execute 1.050s 0.000us 2 2 100.00
progbuf_exception 2 2 100.00
rv_dm_cmderr_exception 1.520s 0.000us 2 2 100.00
rom_read_access 2 2 100.00
rv_dm_rom_read_access 1.080s 0.000us 2 2 100.00
csr_hw_reset 5 5 100.00
rv_dm_csr_hw_reset 2.710s 0.000us 5 5 100.00
csr_rw 20 20 100.00
rv_dm_csr_rw 2.720s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_dm_csr_bit_bash 60.500s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
rv_dm_csr_aliasing 60.170s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_dm_csr_mem_rw_with_rand_reset 4.130s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_dm_csr_aliasing 60.170s 0.000us 5 5 100.00
rv_dm_csr_rw 2.720s 0.000us 20 20 100.00
mem_walk 5 5 100.00
rv_dm_mem_walk 1.040s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
rv_dm_mem_partial_access 0.980s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 2 2 100.00
rv_dm_smoke 8.590s 0.000us 2 2 100.00
jtag_dtm_hard_reset 2 2 100.00
rv_dm_jtag_dtm_hard_reset 1.090s 0.000us 2 2 100.00
jtag_dtm_idle_hint 2 2 100.00
rv_dm_jtag_dtm_idle_hint 1.260s 0.000us 2 2 100.00
jtag_dmi_failed_op 2 2 100.00
rv_dm_dmi_failed_op 1.720s 0.000us 2 2 100.00
jtag_dmi_dm_inactive 2 2 100.00
rv_dm_jtag_dmi_dm_inactive 2.120s 0.000us 2 2 100.00
sba 0 40 0.00
rv_dm_sba_tl_access 651.990s 0.000us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 706.720s 0.000us 0 20 0.00
bad_sba 0 20 0.00
rv_dm_bad_sba_tl_access 804.900s 0.000us 0 20 0.00
sba_autoincrement 0 20 0.00
rv_dm_autoincr_sba_tl_access 668.070s 0.000us 0 20 0.00
jtag_dmi_debug_disabled 0 2 0.00
rv_dm_jtag_dmi_debug_disabled 2.030s 0.000us 0 2 0.00
sba_debug_disabled 2 2 100.00
rv_dm_sba_debug_disabled 4.460s 0.000us 2 2 100.00
ndmreset_req 2 2 100.00
rv_dm_ndmreset_req 1.420s 0.000us 2 2 100.00
hart_unavail 0 5 0.00
rv_dm_hart_unavail 1.490s 0.000us 0 5 0.00
tap_ctrl_transitions 11 11 100.00
rv_dm_tap_fsm_rand_reset 60.500s 0.000us 10 10 100.00
rv_dm_tap_fsm 15.400s 0.000us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.120s 0.000us 1 1 100.00
stress_all 4 50 8.00
rv_dm_stress_all 7590.220s 0.000us 4 50 8.00
alert_test 50 50 100.00
rv_dm_alert_test 1.690s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_dm_tl_errors 5.770s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_dm_tl_errors 5.770s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_dm_csr_aliasing 60.170s 0.000us 5 5 100.00
rv_dm_csr_hw_reset 2.710s 0.000us 5 5 100.00
rv_dm_csr_rw 2.720s 0.000us 20 20 100.00
rv_dm_same_csr_outstanding 8.400s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_dm_csr_aliasing 60.170s 0.000us 5 5 100.00
rv_dm_csr_hw_reset 2.710s 0.000us 5 5 100.00
rv_dm_csr_rw 2.720s 0.000us 20 20 100.00
rv_dm_same_csr_outstanding 8.400s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_dm_tl_intg_err 19.420s 0.000us 20 20 100.00
rv_dm_sec_cm 5.140s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rv_dm_tl_intg_err 19.420s 0.000us 20 20 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 4 4 100.00
rv_dm_sba_debug_disabled 4.460s 0.000us 2 2 100.00
rv_dm_debug_disabled 1.190s 0.000us 2 2 100.00
sec_cm_lc_dft_en_intersig_mubi 4 4 100.00
rv_dm_sba_debug_disabled 4.460s 0.000us 2 2 100.00
rv_dm_debug_disabled 1.190s 0.000us 2 2 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 2 2 100.00
rv_dm_smoke 8.590s 0.000us 2 2 100.00
sec_cm_dm_en_ctrl_lc_gated 9 10 90.00
rv_dm_buffered_enable 1.800s 0.000us 9 10 90.00
sec_cm_sba_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.290s 0.000us 4 4 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.290s 0.000us 4 4 100.00
sec_cm_exec_ctrl_mubi 9 10 90.00
rv_dm_buffered_enable 1.800s 0.000us 9 10 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
rv_dm_stress_all_with_rand_reset 70.800s 0.000us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 680.090s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 25274005187653469127447952674978771421019992214619504470974423168866397777259 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 51851036804860994828684948638778244151850130491961409079682577633299011054554 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 115341800497297857879457289856691921508337843106383471836086094945954695039497 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 40023080849195389132604010418403214300048420877284795856392758505104047014488 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 77967779465331964076338560738388951702663735474797769508696111888505820909395 82
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 17963294308827683022260493079448769391532806673703440425780405367261473729227 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 57052068477805731364463428701464020991448904762378205989681981959374874038541 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 81136530060342681979033583290439760088310535244006041044967533703749353297535 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 21716736553073258606630437908763256532433829418688563243626059042625405785408 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 18092323048417043192221674747152303132908730394475549004234793913638879942247 80
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 29251917612519588088356552676588528538728619066004788969319149301063718463232 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 3551203234356885278803921322524784005308197028392907231215636425394110761054 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 1397429609847141818698535531244130379839033064125953595789020287277624166970 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 56873090742310243252781918662602413757286883257186280734346843527544359099990 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 71918730374164592159437695089109117405639045881014188522077031113822978546452 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 23653902519470892636656747505495497289321904148711393497019899419703410333305 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 12709173155242349037309666857063257877901305549905259948618951461888454539760 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 112950657300483526295525462587514742602298525421329475282796167216191990528613 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 52078684059255047275772998322156621788661956291271844419363353182030103242874 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 61861789941708688538880782882279491781687864192124020916001531315007451288482 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 100565775182596482451005718567980803768062764604793278771409038218933174257716 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 10926229223958263788877867023582362045148314448115226939936467426326069504900 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 73691505057325752828766440236332776839702099353752601844312201860644268474216 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 934179997055023242650614323397222204836954766525190221427802603344888381950 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 114598848883784393179304377801882973219218818164666379630814582439132211738147 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 38709422984138137337371959698485949198924785759048684041052515854415068085444 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 7751188794661662685555168883615289843782600187924977800563990289260176933887 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 16380195817770578786461709838954797721580258096772092004480868204425944156003 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 93366951535617313665377240009363363683334556970465802240425165039874228657746 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 77395154313740749436448063965507828912134504367285556245134109754264009693214 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 15643677755996030800938730311951052609106380515825407560590785452407346866602 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 44889658052941196686400568044911745276766289826675547254742523243541237007791 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 39070804490413991567659145266651761804343921384172286990245408769489418729764 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 112942845419772242787024146786226529397573804768158032131310821183751361272811 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 109881306107173966342196552085222237119660762369577472374376232973767918793138 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 102448770682435878221673864123707346112348529137533035171992819191005441887026 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 14901756358966708343326456391092354478962647079216625056016705525448960716043 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 86123576358062063823284703560490633786172843783721416569464201058195610755275 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 7683847511380899068658775332414664331024695622919421844872211902577986382194 84
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 19854911335417920372547321198411854794340997096158758168109731843174331860060 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 85220180921380401887426254728517117036511385344236943372753870937903062606241 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 63016938998736557402732141513910017933365595044657471749003871820964414862998 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 32231444723673776616413284694526679596558650103238736399259277376432800240707 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 86870202524358041927542187585027508518353899200921893137738761099434105551875 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 103388291271919082319393155841064244473604379520577763562237148866128763014553 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 72306549921629312454668861794559533433345080264893867697294477874676402573102 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 73931105447300692589936612683049677402610400537892751473951450172105503276466 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 42910634068949571157292327535555981934594121288739563050879846507738394471116 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 3688127963033364380291025563552553816619066385306886163923992558236830063849 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 77754055789851112720499163594388074181367657173848434528075192977301585241007 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 50187957032087412340648665789906319063693754532502540823941892778145883227953 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 11768353818780570120703749639785130788610854451844502448926907028203423870786 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 56351668933499460158902142490938556883334888487927919206996746078685792822456 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 9420778135598494165622177021859143766880077940747234165359195382231145144007 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 94147732289798348161949279830427996970071328651761541090210142433170596403918 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 10163785315277874081126927105445787232449873799936450541919346572438527848200 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 66678456826971807448997894420116845708101915326938418394545957080518070554962 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 9182302361702701209395418986400449591745924191326050846872844607007361017753 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 91622884339622767540297366092880062863767252109056697579886076646463038124442 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 73582056956990440856960818665825383667982279152140531121359762068672022052523 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 65512320140552332358419940138846797893497885486407847747296432271776973680992 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 81908342106597562217452307520648608087968766706266164215748144678118805892002 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 22253499573182952070669014842688156620271432998863133928525721305995540109441 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 8575231900119095052522571165750374940684548090954922093241547956823148089736 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 16345288913452144917298276724867220096216020091135296555238181054451876801088 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 107558601068808402444611857827539419935306807299824410904371341284755225916684 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 20704179906424779455041211022283614584267066575361219175010212491312183171979 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 10118467852387443336100305120616429743004976869536507802867073081496940226285 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 100865509089762446795920029169311410954654381856186956902507112408063569974028 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 70099847010503316620865682344709426747371782322282174297898638395206066366901 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 58734095991794497793343522409010289177722740844541112083999491668806353014544 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 66538876869256688041157049382899923145350519285613106847017154063741714906639 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 78454837776923349361216464947296349252079023118639041927691106765213654634915 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 78738613180544449071680901533462780281281604372787198147816362451667950553142 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 105909499154574328334025338926584289332243974981952372781711129087507928302925 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 6967727782568489155759683864727914788840529236385358729102125772901508140403 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 70974306508355454726487397733961563813478299861787777991595522460833750150833 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 32669717632040527874638846617739744878699793393147695504464075953576623930389 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 81913787480065728164659708887994896834278395530475551435502333869546170057643 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 42884238879149261261027378614522859085697502448269204232390144324874220688324 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 38523160822028404855766115800760609106743734824435781502005976276178063582738 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 59765839455752249049134632259230635787641775674425504232731322541189394686573 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 48395048818808750641676933015236485644329312510551733258063030856218585823678 91
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 100870007172558959728659885590650597778146098393654852596388982819556443633693 121
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 101416100404671530481572444840283013828665774793200852582986283287440843114910 78
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 42745734779089488658155952088760852586747924762211663378178002998731804808998 83
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 43184337401843793492992363347177804018497390874334258447533994472238804465213 82
UVM_ERROR @ 117632981 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 117632981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_mem_tl_access_resuming 98528510334188047379281085520617495380120430659084315139955016577820483323250 82
UVM_ERROR @ 425328257 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 425328257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 15478275170271278682126220303336530190663004430924723279447514723806939936146 83
UVM_ERROR @ 604716949 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 604716949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 38062964354160194843058784020004195063176146770594965848276422820502793693934 86
UVM_ERROR @ 1010632100 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1010632100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 15478290200413777231866879037280390844368514154055731635083985643465688773441 84
UVM_ERROR @ 284306441 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 284306441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 11601119110227073283398062477233517417864756688826214780925326016228073875926 96
UVM_ERROR @ 1725733332 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1725733332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 70996274595281504221475841104557687551021709315317921466792790016831967679723 83
UVM_ERROR @ 134741189 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 134741189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 101279043425660230067945118969897791042835055357452052097194440394750700896420 83
UVM_ERROR @ 282166707 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 282166707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 3496852641938445979479814264313711558877790546296370605982381518146581155540 86
UVM_ERROR @ 612647436 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 612647436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 5953955082839551140539911626423141463766038398394473143298079366620868256061 84
UVM_ERROR @ 1649931459 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1649931459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 68446667036591226995136329949817066697184226832807466852097016096115903296054 84
UVM_ERROR @ 1145373901 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1145373901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 105426496594981756559098686097462193633540283610545747209714184391969990348888 98
UVM_ERROR @ 5003058854 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5003058854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 115455880874471424213117001280380324427160963052796011856410618479980480686764 83
UVM_ERROR @ 542651862 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 542651862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 6806455181145751672335872420741781579922192180389371583250734452304379169426 84
UVM_ERROR @ 306873586 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 306873586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 28526153119020425455515333298955557906426015271534760007876888397299992884721 83
UVM_ERROR @ 123596417 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 123596417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 79876317986141578168242863428967890045596172018760374192000707905962224032669 84
UVM_ERROR @ 657639597 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 657639597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 3209767894226226427839305304649804838598295625934886480847328515048237691372 78
UVM_ERROR @ 166569993 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 166569993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 70188502468559685039470454156104507308462209027336959223540663032577233800035 80
UVM_ERROR @ 2097165276 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2097165276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 70377884767719215974768923025277437198958392757921529014063706572971634971146 84
UVM_ERROR @ 1232281563 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1232281563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 93771956508539742317239772565127287164628908588872583819816865373775623063036 82
UVM_ERROR @ 229726796 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 229726796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 72459897809996230004005115738332901020062177069309866035339435722359669832584 91
UVM_ERROR @ 2229113427 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2229113427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 27524890938739856125782666736173797691481152948713104017307906459071898685526 77
UVM_ERROR @ 115241168 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 115241168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 46216087557439942872608166539868085299926758231162968014579258177375758870969 77
UVM_ERROR @ 45442097 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45442097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 96582274363114171158433846320770658611348087324886514233308695694361416741931 82
UVM_ERROR @ 185356025 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 185356025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 4530816471299350813617737632660436399837313996970578420825225025570905163421 82
UVM_ERROR @ 197316875 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 197316875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 50991205183993012193680961940884158946204388444116387763354574031066814882801 96
UVM_ERROR @ 1874368802 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1874368802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 64500450037008773812441862785595290054511768354802132248749110482258922383711 83
UVM_ERROR @ 58529508 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 58529508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 90851479403302054404858203421521716247553177309573124380313068938054904293670 83
UVM_ERROR @ 214781173 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 214781173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 19485351092755446155151096919389396751728614798514490897939802945819736699922 88
UVM_ERROR @ 5354149808 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5354149808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 10255661370900273660718408904998602252827166965966964253126093690895520891818 85
UVM_ERROR @ 349659164 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 349659164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 53527918541909701632892363420724531396264222112110147748998291268437203975090 88
UVM_ERROR @ 1873988484 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1873988484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 90624654610909845057258198042639766802611861248421835854546130508079263563686 84
UVM_ERROR @ 359059132 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 359059132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 40015802860536786186914914812821832418389662166741685603654021242849815078182 80
UVM_ERROR @ 1047341731 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1047341731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 81343773677172458024818537094574584926726887561195642817649787424312017706268 85
UVM_ERROR @ 1215567554 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1215567554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 110997384985499396865168235670595995272570005696808567910277833506177714214006 83
UVM_ERROR @ 298989203 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 298989203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 44823693206975004356746346659915367568768978952088667367291946285537879107924 77
UVM_ERROR @ 182339135 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3725159026 [0xde096a72] vs 0 [0x0])
UVM_INFO @ 182339135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 40836938112161804284161019739257508159394905405118162598849254393175230879011 79
UVM_ERROR @ 1131372937 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (522508353 [0x1f24d841] vs 0 [0x0])
UVM_INFO @ 1131372937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_jtag_dmi_debug_disabled 65567697944767530052086804184281974086610464036795599206364644227302528856853 82
UVM_ERROR @ 558356392 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3531338407 [0xd27bf2a7] vs 0 [0x0])
UVM_INFO @ 558356392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 112219534135863369193501680716642903296066636571378414959924704468203239202720 78
UVM_ERROR @ 139782894 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2922698096 [0xae34d570] vs 0 [0x0])
UVM_INFO @ 139782894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 59649756331583960390278933824222235847186811662138276811018987481984291459959 89
UVM_ERROR @ 443784747 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1868580352 [0x6f604600] vs 0 [0x0])
UVM_INFO @ 443784747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 718681120621811696343400314071225687772110779108643689789301546620447899109 96
UVM_ERROR @ 414545567 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3684888324 [0xdba2ef04] vs 0 [0x0])
UVM_INFO @ 414545567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 54281882038622695899814983450770279250875634516949805690690215539966038714311 83
UVM_ERROR @ 616821265 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2100015400 [0x7d2bb128] vs 0 [0x0])
UVM_INFO @ 616821265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 19670147545685178325710697337013386488855158354865576046127594307533567465590 84
UVM_ERROR @ 399308190 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4232476179 [0xfc467613] vs 0 [0x0])
UVM_INFO @ 399308190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 81137232979091497099550947780169419102146792114544604797475163011121054706112 83
UVM_ERROR @ 556544675 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4070452601 [0xf29e2d79] vs 0 [0x0])
UVM_INFO @ 556544675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 57998666255027557969969252881953019944115477557751337378658459995972704828511 95
UVM_ERROR @ 1149621327 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1977725879 [0x75e1b3b7] vs 0 [0x0])
UVM_INFO @ 1149621327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 685361840892048839023042370292008250853629718295200568223496280889234336545 83
UVM_ERROR @ 369963628 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2235647744 [0x85414700] vs 0 [0x0])
UVM_INFO @ 369963628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 115603796362040019121070373196241126875625853302589153986866754391175991343239 83
UVM_ERROR @ 475673036 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1846474007 [0x6e0ef517] vs 0 [0x0])
UVM_INFO @ 475673036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 37921918120754290048770112333779517853871655977232172242773493077064590484067 83
UVM_ERROR @ 90240061 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3770339492 [0xe0bad0a4] vs 0 [0x0])
UVM_INFO @ 90240061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 100041718309493088502539448503263080257906381635356312156042889468229680787510 83
UVM_ERROR @ 681217380 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3767220259 [0xe08b3823] vs 0 [0x0])
UVM_INFO @ 681217380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 73880514318493202706987754775749669083052125966992854735071694427345453841238 85
UVM_ERROR @ 2308436662 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4064974485 [0xf24a9695] vs 0 [0x0])
UVM_INFO @ 2308436662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 79481065439873060493634647381389291892614473902315227810170130639743861333601 83
UVM_ERROR @ 671903721 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1304298620 [0x4dbe047c] vs 0 [0x0])
UVM_INFO @ 671903721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
rv_dm_stress_all_with_rand_reset 98084628866656006339290348985918906102336881546369665005937398352741866460489 86
UVM_FATAL @ 1498104722 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1498104722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 84346552375010396886788277514068366308002202628505036532721169328439637457648 92
UVM_FATAL @ 1366047759 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1366047759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])
rv_dm_buffered_enable 50316142869221596082152470839770692067679534384961104234557544344501130329714 93
UVM_ERROR @ 273129003 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 273129003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
rv_dm_stress_all 10022003689742739126187442190300807718980533608772648971851107153126457259005 None
Job timed out after 180 minutes
rv_dm_stress_all 90921397980066408277316305682731134728602788853593253943718120429539077336637 None
Job timed out after 180 minutes
rv_dm_stress_all 93150079069236332140587823657573546461893635881423035857316392299923111885372 None
Job timed out after 180 minutes
rv_dm_stress_all 35218588343681165652129492611490597246849960961906215364766729661521388874134 None
Job timed out after 180 minutes
rv_dm_stress_all 9356372679585843977320470808170946623546269833169332695776228319065854136899 None
Job timed out after 180 minutes