Simulation Results

Simulation Results: spi_host

27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.82 %

code
95.06 %

assert
95.64 %

func
90.76 %

block
97.00 %

line
98.76 %

branch
93.45 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.04%
V2S		100.00%
unmapped		100.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	135.000s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	8.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	8.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	9.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	8.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	8.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	8.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	8.000s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	8.000s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	8.000s	0.000us	5	5	100.00

1129/1140 passed

99.04 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	0.000us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	53.000s	0.000us	50	50	100.00
	spi_host_error_cmd	3.000s	0.000us	50	50	100.00
	spi_host_event	271.000s	0.000us	50	50	100.00
clock_rate				48	50	96.00
	spi_host_speed	29.000s	0.000us	48	50	96.00
speed				48	50	96.00
	spi_host_speed	29.000s	0.000us	48	50	96.00
chip_select_timing				48	50	96.00
	spi_host_speed	29.000s	0.000us	48	50	96.00
sw_reset				50	50	100.00
	spi_host_sw_reset	355.000s	0.000us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	0.000us	50	50	100.00
cpol_cpha				48	50	96.00
	spi_host_speed	29.000s	0.000us	48	50	96.00
full_cycle				48	50	96.00
	spi_host_speed	29.000s	0.000us	48	50	96.00
duplex				50	50	100.00
	spi_host_smoke	135.000s	0.000us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	135.000s	0.000us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	103.000s	0.000us	50	50	100.00
spien				50	50	100.00
	spi_host_spien	59.000s	0.000us	50	50	100.00
stall				49	50	98.00
	spi_host_status_stall	175.000s	0.000us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	22.000s	0.000us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	53.000s	0.000us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	0.000us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	8.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	10.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	10.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	8.000s	0.000us	5	5	100.00
	spi_host_csr_rw	8.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	8.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	8.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	8.000s	0.000us	5	5	100.00
	spi_host_csr_rw	8.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	8.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	8.000s	0.000us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_tl_intg_err	8.000s	0.000us	20	20	100.00
	spi_host_sec_cm	2.000s	0.000us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	8.000s	0.000us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	400.000s	0.000us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_speed	77628048438740068455133364876409617108515277820226576995036762755658417347752	311	UVM_FATAL @ 10054479903 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x10875014, Comparison=CompareOpEq, exp_data=0x0, call_count=47 UVM_INFO @ 10054479903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_speed	38965988775491484032916827657128376302576592525395715229150833590394535660958	305	UVM_FATAL @ 10040498934 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xf2f60554, Comparison=CompareOpEq, exp_data=0x0, call_count=63 UVM_INFO @ 10040498934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: spi_host_reg_block.status.rxfull reset value:
	spi_host_status_stall	39592900292433920828457895109606735612862393062094215088790010801169395311808	1561	UVM_ERROR @ 392775750 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0 UVM_INFO @ 392775750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---