Simulation Results

Simulation Results: ac_range_check

03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.32 %

code
93.53 %

assert
97.75 %

func
58.67 %

block
99.10 %

line
99.93 %

branch
98.24 %

toggle
82.43 %

Validation stages

V1		100.00%
V2		98.39%
V2S		100.00%
V3		100.00%
unmapped		100.00%

120/120 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				20	20	100.00
	ac_range_check_smoke	57.000s	0.000us	20	20	100.00
ac_range_check_smoke_racl				20	20	100.00
	ac_range_check_smoke_racl	79.000s	0.000us	20	20	100.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	3.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	45.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	37.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	4.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	3.000s	0.000us	20	20	100.00
	ac_range_check_csr_aliasing	37.000s	0.000us	5	5	100.00

306/311 passed

98.39 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	4.000s	0.000us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	40.000s	0.000us	1	1	100.00
stress_all				45	50	90.00
	ac_range_check_stress_all	315.000s	0.000us	45	50	90.00
alert_test				50	50	100.00
	ac_range_check_alert_test	3.000s	0.000us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	2.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	0.000us	5	5	100.00
	ac_range_check_csr_rw	3.000s	0.000us	20	20	100.00
	ac_range_check_csr_aliasing	37.000s	0.000us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	0.000us	5	5	100.00
	ac_range_check_csr_rw	3.000s	0.000us	20	20	100.00
	ac_range_check_csr_aliasing	37.000s	0.000us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	0.000us	20	20	100.00

V2S

125/125 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	29.000s	0.000us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	29.000s	0.000us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	29.000s	0.000us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	29.000s	0.000us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	140.000s	0.000us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_sec_cm	2.000s	0.000us	5	5	100.00
	ac_range_check_tl_intg_err	15.000s	0.000us	20	20	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	386.000s	0.000us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	50.000s	0.000us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state
	ac_range_check_stress_all	89273893338919683627611583073615628239710438902682054017821631349790628445580	9396	UVM_ERROR @ 11905556702 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 11905556702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	20507176348766727885548699121301534350435623579039981737218313148993016022365	13363	UVM_ERROR @ 2363861392 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2363861392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	6360393877692792082072758472562092703393625246706960918154052634430389667630	4007	UVM_ERROR @ 2258791337 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2258791337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	67946191106294290886416620758853528329730276426668121972303113480264767134820	4707	UVM_ERROR @ 2922990321 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2922990321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
	ac_range_check_stress_all	7307690443207461450623472641350089706479325605477388969559655843671697483199	16640	UVM_ERROR @ 100377149431 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo. UVM_INFO @ 100377149431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---