Simulation Results: alert_handler

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.05 %
  • code
  • 98.91 %
  • assert
  • 98.92 %
  • func
  • 99.32 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.53 %
  • toggle
  • 97.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.64%
V2S
99.09%
V3
64.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 13.540s 0.000us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 13.890s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 529.450s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 270.110s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 17.340s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 13.890s 0.000us 20 20 100.00
alert_handler_csr_aliasing 270.110s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 314.250s 0.000us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 93.830s 0.000us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 3408.440s 0.000us 50 50 100.00
sig_int_fail 48 50 96.00
alert_handler_sig_int_fail 96.020s 0.000us 48 50 96.00
clk_skew 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 76.360s 0.000us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 76.080s 0.000us 50 50 100.00
ping_timeout 20 50 40.00
alert_handler_ping_timeout 579.800s 0.000us 20 50 40.00
lpg 98 100 98.00
alert_handler_lpg 2451.800s 0.000us 48 50 96.00
alert_handler_lpg_stub_clk 3379.660s 0.000us 50 50 100.00
stress_all 50 50 100.00
alert_handler_stress_all 3694.820s 0.000us 50 50 100.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 124.770s 0.000us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.540s 0.000us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.610s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 28.370s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 28.370s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 13.540s 0.000us 5 5 100.00
alert_handler_csr_rw 13.890s 0.000us 20 20 100.00
alert_handler_csr_aliasing 270.110s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 64.960s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 13.540s 0.000us 5 5 100.00
alert_handler_csr_rw 13.890s 0.000us 20 20 100.00
alert_handler_csr_aliasing 270.110s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 64.960s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 366.070s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 366.070s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 366.070s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 366.070s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1379.200s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
alert_handler_tl_intg_err 87.950s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 87.950s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 366.070s 0.000us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 81.140s 0.000us 50 50 100.00
sec_cm_alert_intersig_diff 48 50 96.00
alert_handler_sig_int_fail 96.020s 0.000us 48 50 96.00
sec_cm_lpg_intersig_mubi 48 50 96.00
alert_handler_lpg 2451.800s 0.000us 48 50 96.00
sec_cm_esc_intersig_diff 48 50 96.00
alert_handler_sig_int_fail 96.020s 0.000us 48 50 96.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3408.440s 0.000us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3408.440s 0.000us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 16.850s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 32 50 64.00
alert_handler_stress_all_with_rand_reset 656.250s 0.000us 32 50 64.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 11064928434991639942130161141765162230544244052260622768636673684680320188948 102
UVM_ERROR @ 4007500364 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4007500364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 34747024463390056804782671878702850117342443058208475082300419703273129780673 96
UVM_ERROR @ 10414155620 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 10414155620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 108581579865781645004754650073057735003104084198782665392825591688036089435093 96
UVM_ERROR @ 8813061400 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 8813061400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72873574500738738637266423118940545834184225555442887866838845605784291970979 99
UVM_ERROR @ 2765327765 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 2765327765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 99146841001474069547219249929582406850878950538119067719580803992466287311948 96
UVM_ERROR @ 1806580604 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 1806580604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 48307715700754937010190744861986177374612445332121689144562774831649760788442 162
UVM_ERROR @ 23135089481 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 23135089481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 21637713413709746378139666075184752426670571866052283020152850506564184025762 105
UVM_ERROR @ 8101916914 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 8101916914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 2371281518308578435499117623772341374235210890808565522257260527629375587886 90
UVM_ERROR @ 27417414408 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 27417414408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 36479424684461111235662640174369326301572268234395128654234925272397273369272 114
UVM_ERROR @ 12223253265 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 12223253265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 58416049429417554610362344838846869954891911336695178893339135123094791118509 156
UVM_ERROR @ 70401765492 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 70401765492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 18988457651227083733797480051426581159807977976462240590837118489848670685162 162
UVM_ERROR @ 13721006054 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 13721006054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 109320936246324676239247966267675789092222474144609129656524463800671164552330 112
UVM_ERROR @ 13237823311 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 13237823311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 17684994368997050835850223237996907982089904492455080895411393463114505984457 93
UVM_ERROR @ 12216873596 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 12216873596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 738365249743028538883795658954998612202823364091264932672693616705239811273 163
UVM_ERROR @ 22111184141 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 22111184141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 92739371833541498550504721652292299446445545257822006814708556359944400795965 87
UVM_ERROR @ 2787790655 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2787790655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 70897727178757413432918440394460583791533113262992780326038211849053951885425 129
UVM_ERROR @ 29002754520 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 29002754520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 115727058422272821805033515757875147359749764628336986370737269631344079361882 90
UVM_ERROR @ 5965011187 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 5965011187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 37915478350316163281867483964767256219331791212978718564462993245804161392738 105
UVM_ERROR @ 4753778440 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 4753778440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 112686523580053863740066548821582280244285464797707618717578223734356565444247 84
UVM_ERROR @ 707513256 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 707513256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72872821460576237151919372389511643993675337118321122940402235006624786641656 149
UVM_ERROR @ 10913351500 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 10913351500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72862615751274357576006167907754543761738504456221004469597910100305833255982 90
UVM_ERROR @ 3218543003 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 3218543003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 36703622255033475393383270118855404299760638714376945559272266855040251802750 128
UVM_ERROR @ 1395696644 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1395696644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 71468376816223589176482978016220088558847021247935279333696100419422294577298 93
UVM_ERROR @ 634014063 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 634014063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 18941352064668297760170532788762576482365383271498056158485809071268761056543 128
UVM_ERROR @ 2898257937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2898257937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 17951865570109433935310231836313066702474937010007862509525569339854603510480 133
UVM_ERROR @ 5327061597 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5327061597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 85698754194826326943067735043335170702100411059539119506134330954924064891869 88
UVM_ERROR @ 487493320 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 487493320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 34201404184723465222609916090768822919718601830861361662069806783920476592987 136
UVM_ERROR @ 4246495971 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4246495971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 2331184047839521137525717218072218213107739495412651887705035714367104663864 84
UVM_ERROR @ 363381120 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 363381120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 18532199896797852966136922023868832524208506458676521711758589810752591427595 82
UVM_ERROR @ 173872793 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 173872793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 85333356485003445982359712246866458584160791746738120931420534954601657731160 82
UVM_ERROR @ 625858500 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 625858500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 11828801819970196394183407009561723497979524792687566142532570511344088883181 84
UVM_ERROR @ 114952495 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114952495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 51609541458624837206285810315272501675646583992209940263607121116550271556661 150
UVM_ERROR @ 7041196475 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7041196475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 84200248681766286609491433165850710356582791870486407376911330014423238832851 119
UVM_ERROR @ 6803978453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6803978453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 62987682959390670325276006377659348292882558552255062595548005430447756856128 83
UVM_ERROR @ 141621599 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 141621599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 46568987219672366164969448174290238375033785854229612941757693023082846564736 82
UVM_ERROR @ 457118612 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 457118612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 44234180310408475227473148455356243577710444071203068001166551509377055986280 102
UVM_ERROR @ 1839547733 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1839547733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 100333090896216167681766995319762057755724785144700811224994344395532927771294 92
UVM_ERROR @ 238105567 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 238105567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 8310734160875555039665546606886118565397606989798000081370118402682781764067 130
UVM_ERROR @ 4021095436 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4021095436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:598) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 98870829026801872292430093214822960790328507025199073018181684209291439366149 80
UVM_ERROR @ 5051649999 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5051649999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 115663691678415983750871965152269998677047284323306201155776301910194502114625 80
UVM_ERROR @ 114909582 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 114909582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 48230920990775219163177016382917125674185748224142719241405077988544210132122 80
UVM_ERROR @ 6233868126 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6233868126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72660547945279264759605378543535711619106835517812722776412123539980290075891 80
UVM_ERROR @ 1218538062 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1218538062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 81852169628370842565577046757055523125272024052117004262869929685787924097330 80
UVM_ERROR @ 576802220 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 576802220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 58556228844205521498464355596041961114432502282196583326859323944610502895306 80
UVM_ERROR @ 1714032362 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1714032362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 55265963346015405022574301246244661443522459863035871593951857087560642871343 80
UVM_ERROR @ 558287012 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 558287012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 50190747384466602484592416634345961339985252045344117396695834999871316562511 80
UVM_ERROR @ 109055973423 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 109055973423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 82355589163335908837359164986179036195417076716629548787616385568374437293610 80
UVM_ERROR @ 540511363 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 540511363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 56036907065063138881659624781064924158012774482839732746541535414392498995754 80
UVM_ERROR @ 362483575 ps: (alert_handler_scoreboard.sv:598) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 362483575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)
alert_handler_sig_int_fail 72333273093025812873286006798559265460568280916947502625039806100770257409153 85
UVM_ERROR @ 372613568 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[3]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)
UVM_INFO @ 372613568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_sig_int_fail 88021387381469219127366960929096772468459313264909995536277112325795223606178 81
UVM_ERROR @ 433523253 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[0]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)
UVM_INFO @ 433523253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
alert_handler_lpg 48175015535017347905879635586063581672036299975312567264357437529358148066019 None
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 10988412660571087848039613109448514800613882869799159389310183535509843010296 129
UVM_ERROR @ 2343550545 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2343550545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---