Simulation Results: csrng

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.31 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 90.86 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
93.96%
V2S
99.92%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 5.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 7.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 35.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 5.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 7.000s 0.000us 20 20 100.00
csrng_csr_aliasing 5.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
alerts 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 0.000us 500 500 100.00
cmds 4 50 8.00
csrng_cmds 3516.000s 0.000us 4 50 8.00
life cycle 4 50 8.00
csrng_cmds 3516.000s 0.000us 4 50 8.00
stress_all 46 50 92.00
csrng_stress_all 1388.000s 0.000us 46 50 92.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 0.000us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 8.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 8.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 0.000us 5 5 100.00
csrng_csr_rw 7.000s 0.000us 20 20 100.00
csrng_csr_aliasing 5.000s 0.000us 5 5 100.00
csrng_same_csr_outstanding 4.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 0.000us 5 5 100.00
csrng_csr_rw 7.000s 0.000us 20 20 100.00
csrng_csr_aliasing 5.000s 0.000us 5 5 100.00
csrng_same_csr_outstanding 4.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
csrng_tl_intg_err 11.000s 0.000us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 3.000s 0.000us 50 50 100.00
csrng_csr_rw 7.000s 0.000us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_intersig_mubi 46 50 92.00
csrng_stress_all 1388.000s 0.000us 46 50 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_constants_lc_gated 46 50 92.00
csrng_stress_all 1388.000s 0.000us 46 50 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 11.000s 0.000us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 10.000s 0.000us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 16.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 2.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
csrng_cmds 107278330224964030327291905559695641041935708509332920546339864802192026503026 139
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 26062510060351384226724658868534762602516080163671287678207522677086093323026 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 88893800222705172197475362761022959125711706737449363305851784557286146091653 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 85332392018211766283946256927810244783247714048918312973232381649887872105740 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 24072580272182598253234105716294278112040613745835521673071674588112874237201 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 6125001113215656644758566706043817843767806634601853632543454745621372895182 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 101068559563701027887745366869627490578312610153818518127177971249592049048075 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 76033925321396545004650679249964655636659551873203846241212404919734490725050 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 111777988527788318263927446768017095070537839985215707609298923736397217847831 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 48511193380713065006989302923395452809535545018746226921671154920422207790166 None
Job timed out after 180 minutes
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 18011396937494620045566090055654037722992798228082287231200085993395076621108 130
UVM_FATAL @ 111857877 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 303027031344879736248956142062048392105 [0xe3f8e2240cef234b1916202d3f1433a9])
UVM_INFO @ 111857877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 16542151313447371581711281415191240663548732270611535867224767025847138815339 130
UVM_FATAL @ 301066695 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 144993613855097834945907082801813226890 [0x6d14c117a1c8fcd1836264f6de55858a])
UVM_INFO @ 301066695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4864882067190180705530300703075408781954080404666517863397718565677359574452 130
UVM_FATAL @ 46822238 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 104178613395933543763947700801582980975 [0x4e6012344a7d5d06733d6267b920df6f])
UVM_INFO @ 46822238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 41097555229537016412782599091999195810458956444849225820129806176165384724362 130
UVM_FATAL @ 24726931 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 58039681261627869096913032703300403819 [0x2baa0937fb07d2a6934196d79229026b])
UVM_INFO @ 24726931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 40537249932631939020206155930443499594847168752560918534208531210603681126906 130
UVM_FATAL @ 50416128 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 42584494921410295434374509312365726646 [0x200979b364b176dbdf03f2fb948a8bb6])
UVM_INFO @ 50416128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109739237454012486569488665497580751663786030095802789287900801153989686304348 130
UVM_FATAL @ 67783526 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 124263416704279962057034502880182749911 [0x5d7c437631f26e31a86c71e51e894ad7])
UVM_INFO @ 67783526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48205619774452842100267815169208219570502830088633415605049040734341062494202 130
UVM_FATAL @ 150465764 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 74807299536740364152144552584285489069 [0x38475ca0799eb7c3c079d3fd109387ad])
UVM_INFO @ 150465764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12661080281738309605891049757453861182230711403096316833608641435128622273080 130
UVM_FATAL @ 22780871 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 71728090351245218683708306158469543722 [0x35f653e48c51ef197ed36da9a0d8772a])
UVM_INFO @ 22780871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50605442087675770368971500067698853952846640305688180255872858877671451353390 140
UVM_FATAL @ 507412591 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 180510970553929015019586487358775952321 [0x87cd25fa22cc8b4272e9b9bb9de503c1])
UVM_INFO @ 507412591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110803878639345884632148582378365267495762369002244919494777774664809248943452 130
UVM_FATAL @ 53851095 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 189937064422818229513042898922387017451 [0x8ee48c4935aea9b7f1934d072ca40eeb])
UVM_INFO @ 53851095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108200952943167289959344029457722467472029073489131740397980862237705503224708 140
UVM_FATAL @ 344193879 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 132772129313204828749417845797567673022 [0x63e2fb61e3e2926742499d6cfffd32be])
UVM_INFO @ 344193879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 82281734788226274261383443787264797654672574090750819032648666764022848945407 130
UVM_FATAL @ 41011463 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 31710277157216401592173744526125282618 [0x17db2d5f16bc8b4c2f44b31c093db53a])
UVM_INFO @ 41011463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 101574152288439851134910266570963577550438108940296892238218521282757426241263 130
UVM_FATAL @ 117741706 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 194436280507896175416401631149338360158 [0x924710c3fcfddf92c5d6974b2ceb795e])
UVM_INFO @ 117741706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23802439816911542894739020938167566595929875349398704015074543610276506196404 130
UVM_FATAL @ 74414845 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 311258738694727014031304259569273720534 [0xea2a40a5d5b311b5fbcc08cc72eeced6])
UVM_INFO @ 74414845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110187690829494200402039299321621816675238074661018428911452539125665327122937 130
UVM_FATAL @ 253524375 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 153966808148904771509884180362298802210 [0x73d4edba67c58abcec232978d1e64022])
UVM_INFO @ 253524375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 46698829714652892390333801128709099747439213445007012742723524977608015390283 130
UVM_FATAL @ 304481368 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 172409420027273775533465491142095737326 [0x81b4d8b26be88f1bfef4edaadd4911ee])
UVM_INFO @ 304481368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 20574434887366064824180297721459308257607608292643640328211076942964803854420 130
UVM_FATAL @ 98393307 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 67542592415082647828027435548946869474 [0x32d03ae97f1f8ba5d3b3a98d3d022ce2])
UVM_INFO @ 98393307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 99556955588650203677735205154457659921305884587075788317781546889490440778656 130
UVM_FATAL @ 31044265 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 83160117511026578404356841760004854415 [0x3e900e593fa0ba71feed6c2a2b2d528f])
UVM_INFO @ 31044265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 71268383378834616731409770430317441723036147795008910982520469062948075007846 140
UVM_FATAL @ 432014881 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 122233911106084375798342040911527485948 [0x5bf5651c38bb34e031f6e2c7205721fc])
UVM_INFO @ 432014881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 105905842099463090255382263338275884957511472947602243106282651035504449549477 130
UVM_FATAL @ 58412694 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 313270329955968595561656263129297756030 [0xebadabc1165332b76ab94d538cfe9f7e])
UVM_INFO @ 58412694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 9329155995045511421666454351570130382486147460290417739495938828556250055803 130
UVM_FATAL @ 537143793 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 303523548822000116738800227542249273717 [0xe4588257ac82dbac8f9bb8a71a087975])
UVM_INFO @ 537143793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 27018246368358742042742090190945556706532028065936175451078617879138905907385 130
UVM_FATAL @ 19286081 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 259646038896472971772256893615437296966 [0xc35602147ea7c33a930163285fa4b546])
UVM_INFO @ 19286081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48625952751392251748747335574678384418226789401503935451637391361607771226814 130
UVM_FATAL @ 228573934 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 136262052095118413810769811129658627051 [0x66831ddc355c9e1a7f90643fe7f9d3eb])
UVM_INFO @ 228573934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 55835936928029571950807966890561324304549400038024593053366354327502247566524 130
UVM_FATAL @ 161679272 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 253343981399678584864978160417951118236 [0xbe9846a7fce8fb3d8e9ba593c1d2f39c])
UVM_INFO @ 161679272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 39331140734600533301004730041849235291034536473751667597913984918308798781108 130
UVM_FATAL @ 263797984 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 227766699423056742228754748416369238319 [0xab5a454afa296940a3cc958b3d4a212f])
UVM_INFO @ 263797984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 85681219909350233791558798653938702803637778482126821875699955286689762039950 130
UVM_FATAL @ 62773638 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 17126192974075572848621070066616479644 [0xce262817af530f00f5cb52c210daf9c])
UVM_INFO @ 62773638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 82978058751393563119388553305154721589849373751222275664349888743344382709968 130
UVM_FATAL @ 13881003 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 316809151064324205099367692811592278453 [0xee57391b0df06022d6b5e916833821b5])
UVM_INFO @ 13881003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31765690077296166518877181098604166925950885609435106987866651654462513300165 150
UVM_FATAL @ 665730705 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 241904395612128594275852222905528573974 [0xb5fd1787fe0e787ea36b868ee1276016])
UVM_INFO @ 665730705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 16872807393283726520099213247054469244739868265622773597466032817089339328583 130
UVM_FATAL @ 60727376 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 218273339788077966827727031492582997671 [0xa435ea8692c97b01a277d3be7cba7ea7])
UVM_INFO @ 60727376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 7219347192956704176975825309756186868267901223067873071092695412204752726651 130
UVM_FATAL @ 164020861 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 68090717196276619714546120210665599438 [0x3339cb8cdfa711c60b1ead9ec72a71ce])
UVM_INFO @ 164020861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78114668489926032486633843632261210127058582966548702664047830157837509529106 140
UVM_FATAL @ 488250467 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 180659267175197497385747923282085450540 [0x87e9b590a570f39aa266fb655af6932c])
UVM_INFO @ 488250467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65291606090569152008614709540258953561255040987549987118751407084996691403285 130
UVM_FATAL @ 20808755 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 77642908284900972603404690733711430006 [0x3a697aee9e2eef1527639d42f6cf1176])
UVM_INFO @ 20808755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59850915756924934086572606665140639332073970317573340891626295807854931858782 130
UVM_FATAL @ 203472778 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 80826242244505631474309054600019105724 [0x3cce9169f63992193a2e6c6556ded7bc])
UVM_INFO @ 203472778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106405904465088301754577399595400667418475129668708337358085578410911769934776 130
UVM_FATAL @ 61372510 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 108406644130540489540924523587339636931 [0x518e5c36bb8e907ac5e0454bac6950c3])
UVM_INFO @ 61372510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 55366349706528396514583755752176813417893878398041544172227854964245345891174 130
UVM_FATAL @ 50630355 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 106578634255152281959742035595459657607 [0x502e4c5e54f1f689a4666fbbeb4d7f87])
UVM_INFO @ 50630355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95919253586462272232605296125717834958627141090429293597750083070235926576169 130
UVM_FATAL @ 139092663 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 171308760891920293913847796174730092257 [0x80e0de030826c7c17b29556ce57cdee1])
UVM_INFO @ 139092663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66629465198537168329936677057223793727376579000459851839986636938167384097808 130
UVM_FATAL @ 123683406 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 309190139190657944304173682448678913927 [0xe89bdad165cc53aa9ab3a33b26fa0787])
UVM_INFO @ 123683406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 22149503702269676315383734086167521899196827771078299346287781991612974730903 130
UVM_FATAL @ 102408192 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 141206795163812224046700180210705481197 [0x6a3b708419bc19f1c7a0c86f25d3bded])
UVM_INFO @ 102408192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 87654570609801426673876471218130720592335557628677735879412680244878005085525 140
UVM_FATAL @ 503756081 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 255322230019803824775518870119325571534 [0xc01545d7f18a5bee8a5fda42e8b319ce])
UVM_INFO @ 503756081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits
csrng_cmds 49576734371562679919395619792042127499624072767663060192571889312972374628405 133
UVM_ERROR @ 39440886 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4173290855 [0xf8bf5d67] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 39440886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100289087467162428340088785476284510171038159439942864318019836230153255183669 133
UVM_ERROR @ 203067765 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (759107269 [0x2d3f0ec5] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 203067765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 36362787784455309967396056138116575384960664344065565967636259665418088286948 133
UVM_ERROR @ 229849085 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2192515727 [0x82af228f] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 229849085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73055317290521165109745355756233924291921295189235855766064903786854181194603 133
UVM_ERROR @ 88872032 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2178186487 [0x81d47cf7] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 88872032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started
csrng_stress_all_with_rand_reset 92568528898825552806695527964734197996321325794548637918156973241924428948763 111
UVM_FATAL @ 19735743 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
UVM_INFO @ 19735743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 45513476441676470072950973381530506323584582540626143352462399832965975125152 142
UVM_ERROR @ 616367402 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 616367402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 84671913018808789921532257629029732267539346783559944089080190899409332080997 137
UVM_ERROR @ 1553631794 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1553631794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 83838481137652391835933568736094123458827168486892914265413585839567252021008 143
UVM_ERROR @ 4989635464 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 4989635464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 84800204573391923600010762241938702298802018003531499045736735615727488221314 133
UVM_ERROR @ 28347316 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 28347316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly
csrng_cmds 67672942059853401465462638530166252755012779245333013956065982573800861950656 138
UVM_ERROR @ 174550962 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly
UVM_INFO @ 174550962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*])
csrng_cmds 98108078804762693928979594883184162018673138476215219705386060400097450870854 149
UVM_FATAL @ 111343781 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 1 [0x1])
UVM_INFO @ 111343781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---